Identifying line width errors in integrated circuit designs
AssigneeMicron Technology, Inc.
InventorsChristophe Chevallier, Adriana Ababei
Life of this patent
Estimating the term…
Abstract
A method of identifying line width errors in an integrated circuit design includes adding a line width marker for each of a plurality of lines on a schematic, each line having a schematic line width, creating a layout from the schematic, the layout containing the line width markers and a plurality of layout widths, checking the layout line widths versus the schematic line widths for the plurality of line width marked lines, creating a design representing the layout, the design having a plurality of design line widths, and checking the design line widths versus the layout line widths for the plurality of line width marked lines.
Claims18
A method of identifying line width errors in an integrated circuit design, comprising:
- adding a line width marker for each of a plurality of lines on a schematic, each line having a schematic line width;
- assigning a line width parameter to each line width marker;
- creating a layout from the schematic, the layout containing the line width markers and a plurality of layout widths;
- checking the layout line widths versus the schematic line widths for the plurality of line width marked lines;
- creating a design representing the layout, the design having a plurality of design line widths;
- and
- checking the design line widths versus the layout line widths for the plurality of line width marked lines.
A method of identifying line width errors in an integrated circuit design, comprising:
- adding a line width marker for each of a plurality of schematic lines on a schematic;
- assigning a line width parameter to each line width marker;
- creating a first layout from the schematic having a plurality of layout lines, the layout lines respectively corresponding to the schematic lines;
- checking the first layout versus the schematic to determine where the layout lines are in the first layout;
- creating a second layout including the plurality of layout lines and a width property for each of the layout lines;
- and
- checking the width properties versus the line width parameters.
A method of identifying line width errors in an integrated circuit design, comprising:
- adding a line width marker for each of a plurality of schematic lines on a schematic, each schematic line having a schematic line width;
- assigning a line width parameter to each line width marker;
- creating a layout from the schematic, the layout containing a plurality of layout lines, the layout lines respectively corresponding to the marked schematic lines, each layout line having a layout line width;
- determining whether the schematic matches the layout;
- transferring the width parameter for each line width marker from the schematic to the layout when the schematic matches the layout;
- creating a design representing the layout, the design containing a plurality of design lines, the design lines respectively corresponding to the layout lines, each design line having a design line width;
- checking the design line widths versus the corresponding layout line widths;
- and
- generating an error condition when a design line width is less than a corresponding layout line width.
Dependencies are inferred from the claim text.