US 7,024,618 B2 · Transmission error checking in result forwarding

Abstract

Disclosed is a parity checking scheme for data forwarding of results from a first function unit to a second function unit. In one embodiment, the results of the first function unit are forwarded along a result forwarding bus to a destination parity generator at the second function unit. The destination parity generator generates destination parity bits for the forwarded results and sends the destination parity bits to a parity checking circuit at the second function unit. In addition, the results of the first function unit are sent to a source parity generator at the first function unit. The source parity generator generates source parity bits for the forwarded results and sends the source parity bits to the parity checking circuit at the second function unit via a parity forwarding bus. The parity checking circuit compares the source parity bits and the destination parity bits, and generates a parity error signal indicating whether result forwarding is with any error.

Claims24

Dependent claims

A processor, comprising:

a source function circuit configured to:
receive an operand as input,
perform a first function on the received operand to generate results,
generate source parity bits for the results,
send the results to a destination function circuit via a first forwarding bus prior to or while generating the source parity bits for the results, and
send the source parity bits to the destination function circuit via a second forwarding bus after sending the results to the destination function circuit via the first forwarding bus;
and
a destination function circuit configured to:
receive the results from the source function circuit via the first forwarding bus,
generate destination parity bits for the results,
prior to or while generating the destination parity bits, receive the source parity bits from the source function circuit via the second forwarding bus,
prior to or while the destination parity bits are being generated, perform a second function using the received results, and
compare the source parity bits and the destination parity bits to generate transmission error signals.

10 more elements

A method for checking error of data transmission in a processor, the method comprising the following steps:

generating results, with a source function circuit of the processor, by performing a first function on an operand received by the source function circuit;
generating, with the source function circuit, source parity bits for the results while receiving, with a destination function circuit of the processor, the results from the source function circuit via a first forwarding bus;
sending the source parity bits to the destination function circuit via a second forwarding bus after sending the results to the destination function circuit via the first forwarding bus;
generating, with the destination function circuit, destination parity bits for the results while receiving, with the destination function circuit, the source parity bits from the source function circuit via the second forwarding bus;
prior to or while the destination parity bits are being generated, performing a second function at the destination function circuit using the received results;
and
comparing, with the destination function circuit, the source parity bits and the destination parity bits.

4 more elements

Dependencies are inferred from the claim text.

Transmission error checking in result forwarding

Life of this patent

Transmission error checking in result forwarding

Life of this patent

Abstract

Claims24