DVI link with parallel test data

An information transmission link, comprising:

• a transition minimized differential signaling encoder coupled to receive data from a plurality of first parallel lines to encode the digital data into encoded digital data on a plurality of second parallel lines;
• a pseudo-random binary sequence generator circuit to generate test data on a plurality of third parallel lines;
• a multiplexer coupled to the second parallel lines to receive the encoded digital data and coupled to the third parallel lines to receive the test data, the multiplexer to transmit the encoded digital data on a plurality of fourth parallel lines in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the fourth parallel lines;
• a serializer coupled to the fourth parallel lines to receive and serialize the encoded digital data into encoded and serial digital data in the normal mode of operation and to receive and serialize the test data into serial test data in the test mode of operation, the serializer being coupled to transmit the encoded and serial digital data to a transmission medium in the normal mode of operation and to transmit the serial test data to the transmission medium in the test mode of operation;
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• wherein:
• the test data comprises parallel pseudo-random binary sequence data that repeats every 223-1 clock cycles when in serial form;
• and
• the sequence generator circuit comprises:
• twenty three clocked flip flops each identified by an integer X between 0 and 22, each flip flop comprising a D-type flip flop comprising a D input D<X> and a Q output Q<X>;
• and
• ten exclusive-NOR gates N<Y> wherein Y comprises an integer between 0 and 9 to identify each exclusive-NOR gate N<0> to N<9>, each exclusive-NOR gate N<0> to N<9> comprising a first input, a second input, and an output, wherein:
• the ten Q outputs Q<0> to Q<9> are coupled in parallel to the respective ten D inputs D<10> to D<19>;
• the three Q outputs Q<10> to Q<12> are coupled in parallel to the respective three D inputs D<20> to D<22>;
• the ten D inputs D<0> to D<9> are coupled in parallel to the respective outputs of the exclusive-NOR gates N<0> to N<9>;
• the first inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<8> to Q<17>;
• the second inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<13> to Q<22>;
• and
• the ten Q outputs Q<0> to Q<9> comprise the third parallel lines on which the test data comprising the parallel pseudo-random binary sequence data is generated.

A digital visual interface link comprising:

• a transmitter comprising:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of first parallel lines to encode the digital data into encoded digital data on a plurality of second parallel lines;
• a pseudo-random binary sequence generator circuit to generate test data on a plurality of third parallel lines;
• a multiplexer coupled to the second parallel lines to receive the encoded digital data and coupled to the third parallel lines to receive the test data, the multiplexer to transmit the encoded digital data on a plurality of fourth parallel lines in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the fourth parallel lines;
• a serializer coupled to the fourth parallel lines to receive and serialize the encoded digital data into encoded and serial digital data in the normal mode of operation and to receive and serialize the test data into serial test data in the test mode of operation, the serializer being coupled to transmit the encoded and serial digital data to a transmission medium in the normal mode of operation and to transmit the serial test data to the transmission medium in the test mode of operation;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• a transmission medium coupled to the transmitter to transmit the encoded and serial digital data in the normal mode of operation and to transmit the test data in the test mode of operation;
• and
• a receiver comprising:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

A digital visual interface link comprising:

• a transmitter comprising:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of first parallel lines to encode the digital data into encoded digital data on a plurality of second parallel lines;
• a pseudo-random binary sequence generator circuit to generate test data on a plurality of third parallel lines;
• a multiplexer coupled to the second parallel lines to receive the encoded digital data and coupled to the third parallel lines to receive the test data, the multiplexer to transmit the encoded digital data on a plurality of fourth parallel lines in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the fourth parallel lines;
• a serializer coupled to the fourth parallel lines to receive and serialize the encoded digital data into encoded and serial digital data in the normal mode of operation and to receive and serialize the test data into serial test data in the test mode of operation, the serializer being coupled to transmit the encoded and serial digital data to a transmission medium in the normal mode of operation and to transmit the serial test data to the transmission medium in the test mode of operation;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• a transmission medium coupled to the transmitter to transmit the encoded and serial digital data in the normal mode of operation and to transmit the test data in the test mode of operation;
• and
• a receiver comprising:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data;
• wherein:
• the test data comprises parallel pseudo-random binary sequence data that repeats every 223-1 clock cycles when in serial form;
• and
• the sequence generator circuit comprises:
• twenty three clocked flip flops each identified by an integer X between 0 and 22, each flip flop comprising a D-type flip flop comprising a D input D<X> and a Q output Q<X>;
• and
• ten exclusive-NOR gates N<Y> wherein Y comprises an integer between 0 and 9 to identify each exclusive-NOR gate N<0> to N<9>, each exclusive-NOR gate N<0> to N<9> comprising a first input, a second input, and an output, wherein:
• the ten Q outputs Q<0> to Q<9> are coupled in parallel to the respective ten D inputs D<10> to D<19>;
• the three Q outputs Q<10> to Q<12> are coupled in parallel to the respective three D inputs D<20> to D<22>;
• the ten D inputs D<0> to D<9> are coupled in parallel to the respective outputs of the exclusive-NOR gates N<0> to N<9>;
• the first inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<8> to Q<17>;
• the second inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<13> to Q<22>;
• and
• the ten Q outputs Q<0> to Q<9> comprise the third parallel lines on which the test data comprising the parallel pseudo-random binary sequence data is generated.

An information-handling system comprising:

• a digital visual interface link comprising a transmitter, a receiver, and a transmission medium coupled between the transmitter and the receiver to transmit digital visual information;
• a processor including the transmitter;
• a display unit including the receiver;
• an input/output subsystem;
• a memory device;
• a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem;
• and
• wherein:
• the transmitter comprises:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of first parallel lines to encode the digital data into encoded digital data on a plurality of second parallel lines;
• a pseudo-random binary sequence generator circuit to generate test data on a plurality of third parallel lines;
• a multiplexer coupled to the second parallel lines to receive the encoded digital data and coupled to the third parallel lines to receive the test data, the multiplexer to transmit the encoded digital data on a plurality of fourth parallel lines in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the fourth parallel lines;
• a serializer coupled to the fourth parallel lines to receive and serialize the encoded digital data into encoded and serial digital data in the normal mode of operation and to receive and serialize the test data into serial test data in the test mode of operation, the serializer being coupled to transmit the encoded and serial digital data to a transmission medium in the normal mode of operation and to transmit the serial test data to the transmission medium in the test mode of operation;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• the receiver comprises:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

An information-handling system comprising:

• a digital visual interface link comprising a transmitter, a receiver, and a transmission medium coupled between the transmitter and the receiver to transmit digital visual information;
• a processor including the transmitter;
• a display unit including the receiver;
• an input/output subsystem;
• a memory device;
• a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem;
• and
• wherein:
• the transmitter comprises:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of first parallel lines to encode the digital data into encoded digital data on a plurality of second parallel lines;
• a pseudo-random binary sequence generator circuit to generate test data on a plurality of third parallel lines;
• a multiplexer coupled to the second parallel lines to receive the encoded digital data and coupled to the third parallel lines to receive the test data, the multiplexer to transmit the encoded digital data on a plurality of fourth parallel lines in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the fourth parallel lines;
• a serializer coupled to the fourth parallel lines to receive and serialize the encoded digital data into encoded and serial digital data in the normal mode of operation and to receive and serialize the test data into serial test data in the test mode of operation, the serializer being coupled to transmit the encoded and serial digital data to a transmission medium in the normal mode of operation and to transmit the serial test data to the transmission medium in the test mode of operation;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• the receiver comprises:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data
• wherein:
• the test data comprises parallel pseudo-random binary sequence data that repeats every 223-1 clock cycles when in serial form;
• and
• the sequence generator circuit comprises:
• twenty three clocked flip flops each identified by an integer X between 0 and 22, each flip flop comprising a D-type flip flop comprising a D input D<X> and a Q output Q<X>;
• and
• ten exclusive-NOR gates N<Y> wherein Y comprises an integer between 0 and 9 to identify each exclusive-NOR gate N<0> to N<9>, each exclusive-NOR gate N<0> to N<9> comprising a first input, a second input, and an output, wherein:
• the ten Q outputs Q<0> to Q<9> are coupled in parallel to the respective ten D inputs D<10> to D<19>;
• the three Q outputs Q<10> to Q<12> are coupled in parallel to the respective three D inputs D<20> to D<22>;
• the ten D inputs D<0> to D<9> are coupled in parallel to the respective outputs of the exclusive-NOR gates N<0> to N<9>;
• the first inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<8> to Q<17>;
• the second inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<13> to Q<22>;
• and
• the ten Q outputs Q<0> to Q<9> comprise the third parallel lines on which the test data comprising the parallel pseudo-random binary sequence data is generated.

A method of transmitting data through a link comprising:

• encoding parallel digital data into encoded and parallel digital data in a transition minimized differential signaling encoder;
• generating parallel test data in a pseudo-random binary sequence generator circuit;
• coupling the encoded and parallel digital data through a multiplexer to a serializer in a normal mode of operation;
• coupling the parallel test data through the multiplexer to the serializer in a test mode of operation selected by a test signal coupled to the multiplexer;
• serializing the encoded and parallel digital data into encoded and serial digital data in the serializer in the normal mode of operation;
• serializing the parallel test data into serial test data in the serializer in the test mode of operation;
• transmitting the encoded and serial digital data from the serializer to a transmission medium in the normal mode of operation;
• and
• transmitting the serial test data from the serializer to the transmission medium in the test mode of operation, the multiplexer being fabricated with the encoder, the serializer, and the sequence generator circuit in a single integrated circuit chip.

A method of transmitting data through a link comprising:

• encoding parallel digital into encoded and parallel digital data in a transition minimized differential signaling encoder;
• generating parallel test data in a pseudo-random binary sequence generator circuit;
• coupling the encoded and parallel digital data through a multiplexer to a serializer in a normal mode of operation;
• coupling the parallel test data through the multiplexer to the serializer in a test mode of operation selected by a test signal coupled to the multiplexer;
• serializing the encoded and parallel digital data into encoded and serial digital data in the serializer in the normal mode of operation;
• serializing the parallel test data into serial test data in the serializer in the test mode of operation;
• transmitting the encoded and serial digital data from the serializer to a transmission medium in the normal mode of operation;
• and
• transmitting the serial test data from the serializer to the transmission medium in the test mode of operation, the multiplexer being fabricated with the encoder, the serializer, and the sequence generator circuit in a single integrated circuit chip;
• and
• wherein generating parallel test data further comprises:
• generating parallel pseudo-random binary sequence data that repeats every 223-1 clock cycles when in serial form, the sequence data being generated in a pseudo-random binary sequence generator circuit comprising:
• twenty three clocked flip flops each identified by an integer X between 0 and 22, each flip flop comprising a D-type flip flop comprising a D input D<X> and a Q output Q<X>;
• and
• ten exclusive-NOR gates N<Y> wherein Y comprises an integer between 0 and 9 to identify each exclusive-NOR gate N<0> to N<9>, each exclusive-NOR gate N<0> to N<9> comprising a first input, a second input, and an output, wherein:
• the ten Q outputs Q<0> to Q<9> are coupled in parallel to the respective ten D inputs D<10> to D<19>;
• the three Q outputs Q<10> to Q<12> are coupled in parallel to the respective three D inputs D<20> to D<22>;
• the ten D inputs D<0> to D<9> are coupled in parallel to the respective outputs of the exclusive-NOR gates N<0> to N<9>;
• the first inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<8> to Q<17>;
• the second inputs of the exclusive-NOR gates N<0> to N<9> being coupled in parallel to the respective ten Q outputs Q<13> to Q<22>;
• and
• the ten Q outputs Q<0> to Q<9> comprise the third parallel lines on which the test data comprising the parallel pseudo-random binary sequence data is generated.