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AssigneeAdvanced Micro Devices, Inc.
InventorsChong Chang Lin, Harand Gaspar
Estimating the term…
A method and arrangement is provided for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch. The method includes writing, via the memory interface bus and on a per-bit basis, a first prescribed logic pattern to a prescribed region of the memory to check for one of a bus short to ground and a short between adjacent pins of the memory. The first prescribed logic pattern is read to verify operation of the prescribed region of the memory. The method includes writing, via the memory interface bus and on a per-bit basis, a second prescribed logic pattern, complementary to the first prescribed logic pattern, to a prescribed region of the memory to check for one of a bus short to power and a short between adjacent pins of the memory. The second prescribed logic pattern is read to verify operation of the prescribed region of the memory.
A method of testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch, the method including:
An arrangement for testing memory external to a network switch and a memory interface bus connecting the external memory to the network switch, the arrangement comprising:
Dependencies are inferred from the claim text.