DVI link with circuit and method for test

A digital visual interface link comprising:

• a transmitter comprising:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of parallel lines to encode the digital data into encoded digital data;
• a serializer coupled to receive the encoded digital data from the encoder through a plurality of parallel lines to serialize the encoded digital data into encoded and serial digital data;
• a pseudo-random binary sequence generator circuit to generate test data;
• a multiplexer coupled to receive the encoded and serial digital data from a first line coupled to the serializer and the test data from a second line coupled to the sequence generator circuit, the multiplexer to transmit the encoded and serial digital data in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• a transmission medium coupled to the transmitter to transmit the encoded and serial digital data in the normal mode of operation and to transmit the test data in the test mode of operation;
• and
• a receiver comprising:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

An information-handling system comprising:

• a digital visual interface link comprising a transmitter, a receiver, and a transmission medium coupled between the transmitter and the receiver to transmit digital visual information;
• a processor including the transmitter;
• a display unit including the receiver;
• an input/output subsystem;
• a memory device;
• a bus coupled to the processor, the memory device, the display unit, and the input/output subsystem;
• and
• wherein:
• the transmitter comprises:
• a transition minimized differential signaling encoder coupled to receive digital data from a plurality of parallel lines to encode the digital data into encoded digital data;
• a serializer coupled to receive the encoded digital data from the encoder through a plurality of parallel lines to serialize the encoded digital data into encoded and serial digital data;
• a pseudo-random binary sequence generator circuit to generate test data;
• a multiplexer coupled to receive the encoded and serial digital data from a first line coupled to the serializer and the test data from a second line coupled to the sequence generator circuit, the multiplexer to transmit the encoded and serial digital data to the transmission medium in a normal mode of operation and being coupled to receive a test signal to put the multiplexer in a test mode of operation to transmit the test data to the transmission medium;
• and
• wherein the encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated circuit chip;
• and
• the receiver comprises:
• a deserializer coupled to receive the encoded and serial digital data from the transmission medium to deserialize the encoded and serial digital data into encoded digital data on a plurality of parallel lines;
• and
• a transition minimized differential signaling decoder coupled to receive the encoded digital data from the parallel lines to decode the encoded digital data into digital data.

A method of transmitting data through a link comprising:

• encoding digital data into encoded digital data in a transition minimized differential signaling encoder;
• serializing the encoded digital data into encoded and serial digital data in a serializer;
• generating test data in a pseudo-random binary sequence generator circuit;
• and
• transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation selected by a test signal coupled to the multiplexer, the multiplexer being fabricated with the encoder, the serializer, and the sequence generator circuit in a single integrated circuit chip.