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US 7,024,598 B2Granted
Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits
AssigneeSamsung Electronics Co., Ltd.
InventorsJae-Yong Jeong, Sung-Soo Lee
Life of this patent
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Abstract
A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.
Claims32
A memory device, comprising:
- a plurality of memory cells to store data;
- a data output buffer adapted to operate in a first mode and a second mode, wherein the first mode operates to output data stored in the memory cells;
- a comparator to determine failure of the memory cells to store the data, by comparing the stored data with expected data;
- and
- a fail bit counter for counting the number of those of the memory cells that fail to store data, and for outputting a fail code representing the counted number of the fail bits to the data output buffer, wherein the second mode of the data output buffer operates to output the fail code.
2 more elements
A nonvolatile semiconductor memory device, comprising:
- an array of memory cells arranged in the form of a matrix having rows and columns;
- a row decoder circuit for selecting one of the rows in accordance with a row address;
- a column select circuit for selecting some of the columns in response to a column address and outputting data bits corresponding the selected columns;
- an expected data input buffer circuit for receiving expected data bits supplied from the outside via input/output pins in response to a fail bit detecting command signal;
- a fail bit detecting circuit for operating in response to the fail bit detecting command signal, receiving the expected data bits and the selected data bits, determining failure of the memory cells to store the data, by comparing the selected data bits with the expected data bits, and determining whether the data bits selected by the column select circuit include fail bits, and outputting fail flag signals according to the determination result;
- a fail bit counter and latch circuit for counting the number of the fail bits of the data bits stored in the selected row memory cells in response to the fail flag signals from the fail bit detecting circuit and outputting a fail code representing the counted number of the fail bits;
- and
- a data output buffer adapted to operate in a first mode and a second mode, wherein the first mode operates to output data stored in the memory cells and the second mode operates to output the fail code.
5 more elements
A method for detecting fail bits in a nonvolatile semiconductor memory device, comprising:
- storing test data in memory cells of the device;
- inputting expected data in an expected data buffer of the device;
- comparing the stored expected data with the stored test data to determine failure of the memory cells to store data;
- creating a fall code to registering failure occasions in which the inputted expected data does not correspond with the stored test data;
- outputting data stored in the memory cells from a data output buffer;
- and
- outputting the fail code from the data output buffer.
4 more elements
A method for detecting fail bits in a nonvolatile semiconductor memory device having an array of memory cells, comprising:
- detecting data stored in the array in response to a read command signal;
- selecting some of the detected data bits in response to a column address;
- determining whether the selected data bits each matches corresponding expected data bits applied from the outside;
- counting the number of data bits unmatched in the determining step;
- storing a fail code determined according to the counted number,
- incrementing the column address;
- performing repeatedly the selecting, determining, counting and storing steps until a maximum of the column address is reached;
- outputting data stored in the memory cells from a data output buffer;
- and
- outputting the fail code from the data output buffer.
7 more elements
A nonvolatile semiconductor memory device, comprising:
- an array of memory cells arranged in the form of a matrix having rows and columns;
- a row decoder circuit for selecting one of the rows in accordance with a row address;
- a column select circuit for selecting some of the columns in response to a column address and outputting data bits corresponding the selected columns;
- an expected data input buffer circuit for receiving expected data bits supplied from the outside via input/output pins in response to a fail bit detecting command signal;
- a fail bit detecting circuit for operating in response to the fail bit detecting command signal, receiving the expected data bits and the selected data bits, determining failure of the memory cells to store the data, by comparing the selected data bits with the expected data bits, and determining whether the data bits selected by the column select circuit include fail bits, and outputting fail flag signals according to the determination result, the fail bit detecting circuit generating first and second fail flag signals;
- and
- a fail bit counter and latch circuit for counting the number of the fail bits of the data bits stored in the selected row memory cells in response to the fail flag signals from the fail bit detecting circuit and outputting a fail code representing the counted number of the fail bits, the fail bit counter and latch circuit including:
- a counter for outputting first and second count signal in response to the first fail flag signal, in which the first count signal is activated in pulse corresponding to the first activation of the first fail flag signal and the second count signal is activated in pulse corresponding to the second activation of the second fail flag signal;
- a combination circuit for outputting a set signal by combination of the second count signal and the second fail flag signal;
- and
- a register for activating first fail status signal when the first count signal is activated and second fail status signal when the set signal from the combination circuit is activated.
8 more elements
Dependencies are inferred from the claim text.