Efficient address generation for interleaver and de-interleaver

A communication system, comprising:

• an encoder that encodes a source signal to generate an encoded signal;
• an interleaver that interleaves the encoded signal, thereby generating an encoded, interleaved signal;
• a modulator that modulates the encoded, interleaved signal to generate an encoded, interleaved, modulated signal;
• a communication channel that receives and communicates the encoded, interleaved, modulated signal;
• a demodulator that demodulates the encoded, interleaved, modulated signal to generate a encoded, interleaved, demodulated signal;
• a de-interleaver that de-interleaves the encoded, interleaved, demodulated signal, thereby generating a encoded, de-interleaved, demodulated signal;
• and
• a decoder that decodes the encoded, de-interleaved, demodulated signal to generate an output signal that is a substantial replica of the source signal;
• and
• wherein the interleaver comprises an interleaver starting address register set, an interleaver offset address register set, and an interleaver memory;
• the de-interleaver comprises a de-interleaver starting address register set, a de-interleaver offset address register set and a de-interleaver memory;
• and
• at least one of the interleaver offset address register set and the de-interleaver offset address register set comprises a plurality of values that is operable to be updated.

An interleaver that interleaves a plurality of symbols, the interleaver comprising:

• a memory that stores a plurality of delay lines;
• a starting memory address register set that stores a plurality of starting addresses that corresponds to the plurality of delay lines within the memory;
• an address offset register set that stores a plurality of addresses offsets that corresponds to the plurality of delay lines within the memory;
• a processing circuit that calculates a plurality of row indices;
• and
• wherein a row index within the plurality of row indices is used to identify a location in the memory that corresponds to a delay line within the plurality of delay lines by identifying a starting address within the plurality of starting addresses and an address offsets within the plurality of addresses offsets;
• and
• the identified delay line is used to delay a symbol within the plurality of symbols during the interleaving.

A de-interleaver that de-interleaves a plurality of symbols, the de-interleaver comprising:

• a memory that stores a plurality of delay lines;
• a starting memory address register set that stores a plurality of starting addresses that corresponds to the plurality of delay lines within the memory;
• an address offset register set that stores a plurality of addresses offsets that corresponds to the plurality of delay lines within the memory;
• a processing circuit that calculates a plurality of row indices;
• and
• wherein a row index within the plurality of row indices is used to identify a location in the memory that corresponds to a delay line within the plurality of delay lines by identifying a starting address within the plurality of starting addresses and an address offsets within the plurality of addresses offsets;
• and
• the identified delay line is used to delay a symbol within the plurality of symbols during the interleaving.

A method to perform interleaving of a plurality of symbols, the method comprising:

• calculating a delay line increment based on an interleaver depth value and a block size value;
• using the delay line increment to define a plurality of delay lines that are stored in a memory;
• initializing a plurality of starting memory addresses that corresponds to the plurality of delay lines in the memory;
• initializing a plurality of address offsets that corresponds to the plurality of delay lines in the memory;
• calculating a plurality of row indices;
• identifying a starting address within the plurality of starting addresses and an address offsets within the plurality of addresses offsets by using a row index within the plurality of row indices;
• identifying a location in the memory that corresponds to the identified starting address and the identified address offset;
• performing at least one of reading a symbol from the first location in the memory and writing the symbol into the location;
• and
• wherein the at least one of the reading and the writing of the symbol into the location in the memory incurs a delay to the symbol during the interleaving;
• an interleaver depth value, having a first coefficient, and the block size value, having a second coefficient, are linearly combined thereby summing to a constant value;
• and
• the delay line increment comprises at least one of the first coefficient and the second coefficient.

A method to perform de-interleaving of a plurality of symbols, the method comprising:

• calculating a delay line increment based on an interleaver depth value and a block size value;
• using the delay line increment to define a plurality of delay lines that are stored in a memory;
• initializing a plurality of starting memory addresses that corresponds to the plurality of delay lines in the memory;
• initializing a plurality of address offsets that corresponds to the plurality of delay lines in the memory;
• calculating a plurality of row indices;
• identifying a starting address within the plurality of starting addresses and an address offsets within the plurality of addresses offsets by using a row index within the plurality of row indices;
• identifying a location in the memory that corresponds to the identified starting address and the identified address offset;
• performing at least one of reading a symbol from the first location in the memory and writing the symbol into the location;
• and
• wherein the at least one of the reading and the writing of the symbol into the location in the memory incurs a delay to the symbol during the de-interleaving;
• an interleaver depth value, having a first coefficient, and the block size value, having a second coefficient, are linearly combined thereby summing to a constant value;
• and
• the delay line increment comprises at least one of the first coefficient and the second coefficient.