Configurable timing system having a plurality of timing units interconnected via software programmable registers
AssigneeSTMicroelectronics S.r.l.
InventorAlberto Battaia
Life of this patent
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Abstract
The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The control circuit includes an interface for connection to an external bus to receive and transmit data.
Claims28
A timing system comprising:
- a plurality of timing units to perform a count operation;
- software programmable registers interconnecting the plurality of timing units;
- and
- a control circuit generating at least one clock signal for the plurality of timing units, the control circuit including an interface for connection to an external bus to receive and transmit data.
A timing unit interconnectable with other timing units to define a configurable timing system CTS) for generating digital output signals, and receiving comparison values from a data bus, the timing unit comprising:
- at least one input/output pin;
- a counter;
- a first circuit to generate pulses to be counted by the counter;
- a second circuit to generate start, stop and reset commands for the counter;
- a third circuit connected to the counter to generate the digital output signal, the third circuit comprising
- at least one capture and compare register to store the comparison values,
- a fourth circuit to generate an enabling signal for loading values in the capture and compare register,
- at least one comparator to compare the stored comparison value of the at least one capture and compare register with at least one of a count value of the counter and an external count value, and generate a comparison signal, and
- a logic circuit to generate output digital signals from the comparison signal;
- and
- an output stage to receive the digital output signal and output it on the at least one input/output pin.
A method of performing a timing function in a digital device, the method comprising:
- providing a plurality of timing units to perform a count operation;
- interconnecting the plurality of timing units with software programmable registers;
- and
- generating a clock signal for the plurality of timing units with a control circuit including an interface for connection to an external bus to receive and transmit data.
Dependencies are inferred from the claim text.