Low-power indicator
AssigneeInfineon Technologies North America Corp.
InventorRainer Hoehler
Life of this patent
Estimating the term…
Abstract
A random access memory with a low power mode indicator. The random access memory includes a state machine for generating a power mode output signal. A power mode pin control circuit is connected to the state machine for receiving the power mode output signal. A power mode pin is connected to the power mode pin control circuit for providing an output indicative of the power mode output signal received from the state machine.
Claims35
A random access memory having a low power mode indicator, comprising:
- a state machine for generating a power mode output;
- a power mode pin control circuit connected to the state machine for receiving the power mode output;
- and
- a power mode pin connected to the power mode pin control circuit for providing an output indicative of the power mode output received from the state machine.
A random access memory having a low power mode indicator, comprising:
- a state machine operable to generate a first power mode output signal;
- a power mode decoder connected to the state machine for monitoring the first power mode output signal;
- a power mode output signal generator connected to the power mode decoder for generating a second power mode output signal based on the first power mode output signal;
- and
- a power mode output pin connected to the power mode output signal generator.
A random access memory with a low power mode indicator, comprising:
- control means for generating a current power mode indication of the random access memory;
- and
- power mode pin control means for monitoring the current power mode indication and generating a power mode output signal on a power mode pin based on the current power mode indication from the control means.
A method of providing a power-down indicator in a random access memory, comprising the steps of:
- generating a current power mode indication;
- decoding the current power mode indication;
- and
- generating a power mode output signal on a power mode pin based on the current power mode indication.
A low power mode indicator for a point-to-point connection between an external memory controller and a random access memory, comprising:
- a state machine located in the random access memory for generating a power mode output;
- a power mode decoder connected to the state machine in the random access memory for receiving the power mode output;
- a power mode output generator connected to the state machine in the random access memory for generating a power mode output indication based on the power mode output from the state machine;
- a power mode output pin connected to the power mode output generator and located on the random access memory;
- and
- where the external memory controller is connected to the power pin for receiving the power mode output indication from the power mode output generator.
A random access memory having a low power mode indicator, comprising:
- a state machine for generating a power mode output;
- a power mode pin control circuit connected to the state machine for receiving the power mode output;
- a power mode pin connected to the power mode pin control circuit for providing an output indicative of the power mode output received from the state machine;
- and
- a register for storing a power mode variable indicative of a current power mode of the random access memory.
A random access memory having a low power mode indicator, comprising:
- a state machine for generating a power mode output;
- a power mode pin control circuit connected to the state machine for receiving the power mode output;
- and
- a power mode pin connected to the power mode pin control circuit for providing an output indicative of the power mode output received from the state machine,
- wherein the output is generated using a digital logic level.
A random access memory having a low power mode indicator, comprising:
- a state machine operable to generate a first power mode output signal;
- a power mode decoder connected to the state machine for monitoring the first power mode output signal;
- a power mode output signal generator connected to the power mode decoder for generating a second power mode output signal based on the first power mode output signal;
- a power mode output pin connected to the power mode output signal generator;
- and
- a register for storing a power mode variable indicative of a current power mode of the random access memory.
A random access memory having a low power mode indicator, comprising:
- a state machine operable to generate a first power mode output signal;
- a power mode decoder connected to the state machine for monitoring the first power mode output signal;
- a power mode output signal generator connected to the power mode decoder for generating a second power mode output signal based on the first power mode output signal;
- and
- a power mode output pin connected to the power mode output signal generator,
- wherein the second power mode output signal is generated as a digital logic output signal.
A random access memory with a low power mode indicator, comprising:
- control means for generating a current power mode indication of the random access memory;
- power mode pin control means for monitoring the current power mode indication and generating a power mode output signal on a power mode pin based on the current power mode indication from the control means;
- and
- storage means for storing a power mode variable indicative of a current power mode of the random access memory.
A random access memory with a low power mode indicator, comprising:
- control means for generating a current power mode indication of the random access memory;
- and
- power mode pin control means for monitoring the current power mode indication and generating a power mode output signal on a power mode pin based on the current power mode indication from the control means,
- wherein the power mode output signal is generated as a digital logic output signal.
Dependencies are inferred from the claim text.