Systems and methods that authorize target devices utilizing proprietary software and/or hardware

An authorization device, comprising:

• an integrated circuit component responsive to a first data stream that varies in time during a first time interval, said integrated circuit component configured to perform an encryption operation on at least a portion of the first data stream to thereby generate a second encrypted data stream that is time-varying and at least periodically evaluated during the first time interval to assess whether operation of a programmable logic device is authorized during the first time interval;
• wherein said integrated circuit component comprises circuitry that intentionally inserts errors into the second encrypted data stream in sufficient quantity to inhibit reverse-engineering of the encryption operation;
• and
• wherein the encryption operation generates a first permuted bit as a function of a first bit in the first data stream and at least a first encrypted bit in the second encrypted data stream.

An authorization device, comprising:

• an integrated circuit component that in response to a first data stream generates a second encrypted data stream which is at least periodically evaluated during a first time interval to assess whether operation of a programmable logic device during the first time interval is authorized;
• wherein the first data stream and the second encrypted data stream are time division multiplexed on an I/O pin associated with said integrated circuit component;
• wherein said integrated circuit component utilizes an encryption operation to generate the second encrypted data stream from the first data stream;
• wherein the encryption operation generates a first permuted bit as a function of a first bit in the first data stream and at least a first encrypted bit in the second encrypted data stream;
• and
• wherein the encryption operation uses an encryption key to generate a second encrypted bit in the second encrypted data stream from at least the first permuted bit.

An integrated system, comprising:

• an authorization device configured to generate a first encrypted data stream that is time-varying during a first time interval;
• a programmable logic device configured to generate a second encrypted data stream, which is time-varying during the first time interval, while simultaneously operating under at least partial control of configuration data during the first time interval;
• and
• authorization detection circuitry configured to at least periodically compare the first and second encrypted data streams at multiple points during the first time interval and further configured to disable operation of said programmable logic device if the first and second encrypted data streams indicate that said programmable logic device is not authorized to utilize the configuration data during the first time interval.

An integrated system, comprising:

• an authorization device configured to generate a first encrypted data stream that is time-varying during a first time interval;
• a programmable logic device configured to generate a second encrypted data stream, which is time-varying during the first time interval, while simultaneously operating under at least partial control of configuration data during the first time interval;
• and
• authorization detection circuitry configured to at least periodically compare the first and second encrypted data streams at multiple points during the first time interval and further configured to disable operation of said programmable logic device if the first and second encrypted data streams indicate that said programmable logic device is not authorized to utilize the configuration data during the first time interval;
• wherein said programmable logic device generates an at least weakly random data stream during the first time interval;
• wherein said authorization device generates the first encrypted data stream in response to the at least weakly random data stream;
• wherein said authorization detection circuitry operates as a dead man switch internal to said programmable logic device;
• wherein said programmable logic device utilizes an encryption operation to generate the second encrypted data stream;
• and
• wherein each of a plurality of bits in the second encrypted data stream is determined by performing the encryption operation on at least one respective bit in the first encrypted data stream and at least one respective bit in the at least weakly random data stream.

An integrated system, comprising:

• an authorization device configured to generate a first time-varying encrypted data stream during a first time interval;
• an integrated circuit device configured to generate a second time-varying encrypted data stream and perform first operations during the first time interval;
• and
• authorization detection circuitry that at least periodically compares the first and second time-varying encrypted data streams at multiple points during the first time interval and disables operation of said integrated circuit device if the first and second time-varying encrypted data streams indicate that said integrated circuit device is not authorized to perform the first operations.

An integrated system, comprising:

• an authorization device configured to generate a first time-varying encrypted data stream during a first time interval;
• an integrated circuit device configured to generate a second time-varying encrypted data stream and perform first operations during the first time interval;
• and
• authorization detection circuitry that at least periodically compares the first and second time-varying encrypted data streams at multiple points during the first time interval and disables operation of said integrated circuit device if the first and second time-varying encrypted data streams indicate that said integrated circuit device is not authorized to perform the first operations;
• wherein said integrated circuit device generates an at least weakly random data stream during the first time interval;
• wherein said authorization device generates the first time-varying encrypted data stream in response to the at least weakly random data stream;
• wherein said authorization detection circuitry operates as a dead man switch internal to said integrated circuit device;
• wherein said integrated circuit device utilizes an encryption operation to generate the second time-varying encrypted data stream;
• and
• wherein each of a plurality of bits in the second time-varying encrypted data stream is determined by performing the encryption operation on at least one respective bit in the first time-varying encrypted data stream and at least one respective bit in the at least weakly random data stream.

A method of operating a programmable logic device, comprising the steps of:

• generating first and second encrypted data streams in first and second devices, respectively, while simultaneously operating the programmable logic device configured to perform a first operation during a first time interval;
• evaluating the first and second encrypted data streams at least periodically during the first time interval and disabling operation of the programmable logic device during a subsequent second time interval if a comparison of the first and second data streams indicate that the programmable logic device is not authorized to perform the first operation;
• and
• generating an at least weakly random data stream during the first time interval;
• wherein the first and second encrypted data streams are generated from the at least weakly random data stream;
• wherein the first encrypted data stream is generated internal to the programmable logic device and the second encrypted data stream is generated external to the programmable logic device;
• wherein the at least weakly random data stream is generated internal to the programmable logic device;
• wherein the at least weakly random data stream is provided by a single wire bus to a device external to the programmable logic device;
• and
• wherein the at least weakly random data stream is time division multiplexed on the bus with the second encrypted data stream.

An authorization device, comprising:

• a first integrated circuit component that in response to a first data stream generated external to said first component generates a second data stream that is at least periodically evaluated by a distinct second integrated circuit component to assess whether performance of operations within the second integrated circuit component are authorized during a time interval when the first data stream is being generated;
• wherein the second data stream is an encrypted data stream;
• and
• wherein each of a plurality of bits within the second data stream is generated within said first integrated circuit component using an encryption operation that is a function of at least one bit in the first data stream and at least one bit in the second data stream.

An authorization device, comprising:

• a first integrated circuit component that in response to a first data stream generated external to said first component generates a second data stream that is at least periodically evaluated by a distinct second integrated circuit component to assess whether performance of operations within the second integrated circuit component are authorized during a time interval when the first data stream is being generated;
• wherein the second data stream is an encrypted data stream;
• and
• wherein a first encrypted bit within the second data stream is generated within said first integrated circuit component using an encryption operation that is a function of at least one bit in the first data stream and a plurality of previously generated encrypted bits in the second data stream.

An integrated circuit system, comprising:

• a first component that in response to a first data stream generated external to said first component generates a second encrypted data stream;
• and
• a second component that at least periodically evaluates the second encrypted data stream to assess whether performance of at least one operation within the second component is authorized during a time interval when the first data stream is being generated;
• wherein said second component generates the first data stream;
• wherein said first and second components comprise first and second stream encryptors therein, respectively;
• wherein the second encryptor within said second component generates a third encrypted data stream;
• and
• wherein said second component comprises circuitry that operates as a deadman switch to disable performance of the at least one operation within said second component if the second and third encrypted data streams fail to indicate that said second component is authorized by said first component to perform the at least one operation.