Method and apparatus for updating boot code using a system controller

Apparatus comprising a service processor and multiple computing subsystems, each subsystem including:

• a central processing unit (CPU);
• a programmable memory including boot code at a predetermined location for use in booting the CPU;
• a bus;
• a bus master for the bus, wherein the CPU is configured to access the boot code via said bus and said bus master;
• a buffer coupled to the bus, wherein the buffer is configured to support a JTAG interface;
• and
• a system controller, wherein the system controller is operable to receive boot code from the service processor and to write the received boot code into the programmable memory of the subsystem over said bus.

Apparatus comprising:

• a central processing unit (CPU);
• a bus;
• and
• single-port static random access memory (SRAM) attached to the bus;
• wherein the apparatus is configured for the CPU to boot by accessing over said bus boot code stored at a predetermined location within said SRAM;
• and
• wherein the SRAM is also configured to serve as a scratchpad memory for use by the CPU during booting, wherein said SRAM is divided into two regions, a first region for storing boot code and a second region for use as the scratchpad memory.

A method of operating apparatus comprising a service processor and multiple computing subsystems, each subsystem including a central processing unit (CPU), a programmable memory, a bus, a bus master for the bus, a buffer coupled to the bus, and a system controller, wherein the buffer is configured to support a JTAG interface and includes a JTAG control link from the system controller, the method comprising:

• the service processor transmitting boot code to each of the system controllers;
• the system controller transmitting, over the JTAG control link to the buffer, boot code to write into a predetermined location of the programmable memory of the subsystem over said bus;
• and
• the CPU accessing the boot code from the programmable memory via the bus master and the bus in order to boot the CPU.

Apparatus comprising:

• a central processing unit (CPU);
• a programmable memory including boot code at a predetermined location for use in booting the CPU;
• a bus;
• a bus master for the bus, wherein the CPU is configured to access the boot code via said bus and said bus master;
• and
• a system controller, wherein the system controller is operable to write boot code into the programmable memory over said bus;
• wherein said programmable memory includes a memory configured to serve as a scratchpad memory for use by the CPU during booting, wherein said memory is divided into two regions, a first region for storing boot code and a second region for use as the scratchpad memory.

Apparatus comprising:

• a central processing unit (CPU);
• a programmable memory including boot code at a predetermined location for use in booting the CPU;
• a bus;
• a bus master for the bus, wherein the CPU is configured to access the boot code via said bus and said bus master;
• a program logic device (PLD) coupled to the bus;
• and
• a system controller, wherein the system controller is operable to write boot code into the programmable memory over said bus;
• wherein said programmable memory includes static random access memory (SRAM) configured to serve as a scratchpad memory for use by the CPU during booting;
• wherein the PLD is operable to redirect bus transactions for the scratchpad memory to the SRAM.