Hybrid branch prediction device with two levels of branch prediction cache

A branch prediction mechanism comprising:

• a first level cache configured to store branch prediction information;
• a second level cache configured to store a subset of said branch prediction information;
• circuitry coupled to said first level cache and said second level cache, wherein said circuitry is configured to:
• detect said first level cache does not contain a first branch prediction information corresponding to a fetch address;
• determine whether said second level cache contains a second branch prediction information corresponding to said fetch address, said second branch prediction information comprising a subset of said first branch prediction information;
• and
• rebuild said first branch prediction information in response to determining said second level cache contains said second branch prediction information, wherein in order to rebuild said first branch prediction information, said circuitry is configured to:
• receive said second branch prediction information;
• receive a group of instructions corresponding to the fetch address;
• utilize the second branch prediction information to identify one or more predicted taken branches within the group of instructions;
• generate third branch prediction information by decoding each of the identified one or more predicted taken branches to determine a type of each of the one or more predicted taken branches, and determining a size of any immediate or displacement data for each of the one or more predicted taken branches;
• and
• combine said second branch prediction information with said third branch prediction information;
• store said combined second and third branch prediction information as said first branch prediction information in a first entry of said first level cache, wherein said first entry corresponds to said fetch address.

A computer system comprising:

• an interconnect;
• a memory coupled to said interconnect;
• a second level cache configured to store branch prediction information;
• a processor including a first level cache, wherein said processor is configured to:
• detect said first level cache does not contain a first branch prediction information corresponding to a fetch address;
• determine whether said second level cache contains a second branch prediction information corresponding to said fetch address, said second branch prediction information comprising a subset of said first branch prediction information;
• rebuild said first branch prediction information in response to determining said second level cache contains said second branch prediction information, wherein in order to rebuild said first branch prediction information, said processor is configured to:
• receive said second branch prediction information;
• receive a group of instructions corresponding to the fetch address;
• utilize the second branch prediction information to identify one or more predicted taken branches within the group of instructions;
• generate third branch prediction information by decoding each of the identified one or more predicted taken branches to determine a type of each of the one or more predicted taken branches, and determining a size of any immediate or displacement data for each of the one or more predicted taken branches;
• and
• combine said second branch prediction information with said third branch prediction information;
• store said combined second and third branch prediction information as said first branch prediction in a first entry of said first level cache, wherein said first entry corresponds to said first address.