Processor multiple function units executing cycle specifying variable length instruction block and using common target block address updated pointers

A data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in said program defining an instruction that is to be executed if that branch instruction causes said program to branch, said data processing system comprising:

• a plurality of processing sections, each processing section comprising:
• a local memory for storing instruction sequences from said program that are to be executed by that processing section, said instruction sequences comprising instructions of different lengths;
• a function unit for executing instructions stored in said local memory;
• and
• a pointer containing a value defining the next instruction in said local memory to be executed by said function unit, wherein each processing section executes part of said program;
• each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle;
• and
• said pointers in each of said processing sections are reset to a new value determined by said target address of one of said branch instructions when a function unit branches in response to that branch instruction.