Host adapter integrated data FIFO and data cache and method for improved host adapter sourcing latency

A method comprising:

• maintaining a queue of host adapter hardware control blocks for which caching of data is to be performed;
• removing a host adapter hardware control block from said queue upon a first I/O bus data transfer module becoming available;
• enabling said first I/O bus data transfer module to transfer data specified in said host adapter hardware control block;
• asserting a flag in said host adapter hardware control block indicating said enabling;
• caching said data in a memory of a host adapter interfacing a first I/O bus and a second I/O bus by using said first I/O bus data transfer module to transfer said data to said memory;
• and
• transferring said data, concurrently with said caching, from said memory.

A method comprising:

• loading a pointer to a hardware control block in an execution queue of a host adapter interfacing a first I/O bus and a second I/O bus;
• loading another pointer to said hardware control block in an enable caching queue of said host adapter;
• removing said another pointer to said hardware control block from said enable caching queue upon a first I/O bus data transfer module becoming available;
• and
• enabling said first I/O bus data transfer module to transfer data from said first I/O bus to a data first-in-first-out (FIFO)/caching memory of said host adapter following said removing said another pointer;
• asserting a flag in said hardware control block to indicate said enabling said first I/o bus data transfer module;
• caching data in said data FIFO/caching memory by transferring said data from said first I/O bus to said data FIFO/caching memory using said first I/O bus data transfer module following said enabling;
• removing said pointer to said hardware control block from said execution queue;
• determining whether said flag in said hardware control block is asserted;
• and
• transferring said data from said data FIFO/caching memory upon said determining finding that said flag in said hardware control block is asserted.

A host adapter comprising:

• a first I/O bus data transfer module;
• a second I/O bus data transfer module;
• a data first-in-first-out (FIFO)/caching memory coupled to said first I/O bus data transfer module and to said second I/O bus data transfer module;
• and
• a throttle control module coupled to said first I/O bus data transfer module, to said second I/o bus data transfer module, and to said data FIFO/caching memory, wherein said throttle control module controls data transfer from said data FIFO/caching memory by said second I/O bus data transfer module as data is concurrently being transferred into said data FIFO/caching memory using said first I/O bus data transfer module.

A system comprising:

• a first I/O bus;
• a second I/O bus;
• and
• a host adapter comprising:
• a first I/O bus data transfer module coupled to said first I/O bus;
• a second I/O bus data transfer module coupled to said second I/O bus;
• a data first-in-first-out (FIFO)/caching memory coupled to said first I/O bus data transfer module and to said second I/O bus data transfer module;
• and
• a throttle control module coupled to said first I/O bus data transfer module, to said second I/O bus data transfer module, and to said data-FIFO/caching memory, wherein said throttle control module controls data transfer from said data FIFO/caching memory by said second I/O bus data transfer module as data is concurrently being transferred into said data FIFO/caching memory using said first I/O bus data transfer module.