US 7,024,520 B2 · System and method enabling efficient cache line reuse in a computer system

Abstract

A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.

Claims20

Dependent claims

An apparatus for use with a computer system having a plurality of processors and a shared memory accessible by the processors, the shared memory organized into a plurality of memory blocks, each processor having a cache with a plurality of lines for storing selected memory blocks, the apparatus comprising:

a duplicate tag (DTAG) that holds information for a given processor, the DTAG having first and second regions, each of the first and second regions having a plurality of entries, and each entry of each region stores an address and one or more states for a cache line at the given processor, whereby for each of a plurality of cache lines at the given processor there is a matching entry in both the first and the second DTAG regions;
and
a controller operatively coupled to the DTAG, wherein
the controller loads the address and the one or more states into the DTAG entries of the first and second regions, and
for each of two or more cache lines, the address loaded into the two matching entries at the first and second regions is different.

2 more elements

A method for use with a computer system having a plurality of processors and a shared memory accessible by the processors, the shared memory organized into a plurality of memory blocks, each processor having a cache organized into a plurality of lines for storing selected memory blocks, the method comprising:

providing a duplicate tag (DTAG) for the cache of a given processor;
providing two separate entries in the DTAG for each cache line;
and
for a given cache line, entering a first address in the first DTAG entry for the given cache line, and a second address in the second DTAG entry for the given cache line, whereby
the first and second addresses are different.

2 more elements

Dependencies are inferred from the claim text.

System and method enabling efficient cache line reuse in a computer system

Life of this patent

System and method enabling efficient cache line reuse in a computer system

Life of this patent

Abstract

Claims20