Methods and apparatus for controlling hierarchical cache memory
AssigneeSony Computer Entertainment Inc.
InventorHidetaka Magoshi
Life of this patent
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Abstract
Methods and apparatus for controlling hierarchical cache memories permit: controlling a first level cache memory including a plurality of cache lines, each cache line being operable to store an address tag and data; controlling a next lower level cache memory including a plurality of cache lines, each cache line being operable to store an address tag, status flags, and data, the status flags of each cache line including an L-flag; and setting the L-flag of a given cache line of the next lower level cache memory to indicate whether or not a corresponding one the of the cache lines of the first level cache memory has been refilled with a copy of the data stored in the given cache line of the next lower level cache memory.
Claims21
An apparatus, comprising:
- a first level cache memory including a plurality of M1 cache lines, each cache line being operable to store an address tag and data;
- a next lower level N-way set associative unified cache memory, each of the N-way sets including a plurality of M2 cache lines, each cache line being operable to store an address tag, status flags, and data, and M2 being greater than M1;
- and
- an additional memory associated with the next lower level cache memory and including a plurality of M1 memory lines, each memory line including respective L-flags for multiple cache lines of each N way set of the next lower level cache memory, each L-bit flag indicating whether any of the cache lines of the first level cache memory contain a copy of the data stored in the given cache line of the next lower level cache memory,
- wherein the number of L-flags in each memory line of the additional memory is equal to M2 /M1*N.
A method, comprising:
- controlling a first level cache memory including a plurality of M1 cache lines, each cache line being operable to store an address tag and data;
- controlling a next lower level N-way set associative unified cache memory, each of the N-way sets including a plurality of M2 cache lines, each cache line being operable to store an address tag, status flags, and data, and M2 being greater than M1;
- controlling an additional memory associated with the next lower level cache memory and including a plurality of M1 memory lines, each memory line including respective L-flags for multiple cache lines of each N way set of the next lower level cache memory;
- and
- setting the respective L-flags of the additional memory to indicate whether or not corresponding cache lines of the first level cache memory have been refilled with data stored in the cache lines of the next lower level cache memory,
- wherein the number of L-flags in each memory line of the additional memory is equal to M2 /M1*N.
Dependencies are inferred from the claim text.