Method and apparatus for active memory bus peripheral control utilizing address call sequencing

A method to initiate, by a host, an event in a first device comprising:

• communicating, by a signal line, a plurality of values between a host and one or more second devices;
• communicating, by a tap line, said plurality of values between said signal line and said first device;
• initiating said event upon detection by said first device of a predetermined sequence of address locations on the tap line;
• and
• selectively switching a communication path from a third device to one of the host and the first device, in response to said detection.

A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to initiate, by a host, an event in a first device comprising:

• communicating, by a signal line, a plurality of values between a host and one or more second devices;
• communicating, by a tap line, said plurality of values between said signal line and said first device;
• initiating said event upon detection by said first device of a predetermined sequence of address locations on the tap line;
• and
• selectively switching a communication path from a third device to one of the host and the first device, in response to said detection.

A system comprising:

• a first device to execute a variety of computationally intensive tasks;
• a memory bus directly coupled to both a host and one or more second devices, the memory bus to communicate a plurality of data values between the host and said one or more second devices;
• a tap line to communicate said plurality of data values between the memory bus and the first device;
• and
• a memory device selectively coupled, by a bus switch line, to one of the host and first device, wherein the bus switch line is coupled with the memory device and the bus switch line is selectively switched between the first device and the host in response to an event initiation, wherein the tap line communicatively connects the first device with the host via the memory bus, and wherein a sequence of control signals sent from the host to the first device cause an event initiation, wherein the sequence of control signals comprise a sequence of address locations.

A system comprising:

• a first device to execute a variety of computationally intensive tasks;
• a memory bus to communicate a plurality of values between a host and one or more second devices;
• a tap line to communicate said plurality of values between the memory bus and the first device, wherein the tap line communicatively connects the first device with the host via the memory bus, and wherein a sequence of control signals comprising a sequence of address locations is sent from the host to the first device to cause an event initiation;
• and
• a memory device selectively coupled, by a bus switch line, to one of the host and first device, wherein the bus switch line is coupled with the memory device and the bus switch line is selectively switched between the first device and the host in response to the event initiation.