US 7,024,509 B2 · Passive release avoidance technique

Abstract

A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled. After forwarding the first message to the I/O device, the bridge port forwards the second message to the interrupt controller so that the interrupt can be deasserted before the interrupt pending flag is cleared.

Claims17

Dependent claims

A method for preventing passive release of interrupts within a computer system, the computer system having at least one processor for servicing the interrupts, one or more input/output (I/O) devices configured to issue interrupts, and an I/O bridge having a plurality of ports to which I/O devices are coupled and configured to interface between the I/O devices and the processor, the method comprising the steps of:

asserting an interrupt signal by a subject I/O device coupled to a given port of the I/O bridge;
forwarding an interrupt message corresponding to the interrupt signal to the processor for servicing;
setting an interrupt pending flag in response to assertion of the interrupt signal;
in response to the interrupt being serviced, generating a first ordered message, the first ordered message notifying the subject I/O device that the interrupt has been serviced;
generating a second ordered message for clearing the interrupt pending flag;
sending the first ordered message to the given port of the I/O bridge;
sending the second ordered message to the given port of the I/O bridge after the first message has been sent;
deasserting the interrupt signal in response to the first message;
and
clearing the interrupt pending flag in response to the second ordered message.

7 more elements

A computer system comprising:

a plurality of input/output (I/O) devices configured to assert and deassert respective interrupt signals;
at least one processor for servicing interrupts from the I/O devices;
and
an I/O bridge configured to interface between the I/O devices and the at least one processor, the I/O bridge having a plurality of ports to which the I/O devices are coupled and an interrupt controller configured to detect the assertion and deassertion of the interrupt signals, wherein
the interrupt controller, in response to assertion of an interrupt signal by a subject I/O device coupled to a given port of the I/O bridge, issues an interrupt message to the at least one processor and sets an interrupt pending flag;
the at least one processor, upon servicing the interrupt, sends first and second ordered messages to the given port of the I/O bridge, the first ordered message notifying the subject I/O device that the interrupt has been serviced, and the second ordered message clearing the interrupt pending flag;
the subject I/O device deasserts the interrupt signal in response to the first message;
and
the interrupt pending flag is cleared in response to the second ordered message.

6 more elements

Dependencies are inferred from the claim text.

Passive release avoidance technique

Life of this patent

Passive release avoidance technique

Life of this patent

Abstract

Claims17