Split multiplier array and method of operation
AssigneeNational Semiconductor Corporation
InventorDaniel W. Green
Life of this patent
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Abstract
There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split array for adding the partial products. A first summation array comprises a first group of adders that sum the even partial products to produce an even summation value. A second summation array comprises a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.
Claims21
A multiplier circuit, comprising:
- a partial products generator capable of receiving a multiplicand value and a multiplier value and generating a plurality of partial products;
- a first summing array capable of summing a first subset of the partial products to produce a first summation value;
- and
- a second summing array capable of summing a second subset of the partial products to produce a second summation value;
- wherein at least one of:
- at least some of the partial products in the first subset are non-sequential ones of the plurality of partial products;
- and
- at least some of the partial products in the second subset are non-sequential ones of the plurality of partial products.
A data processor, comprising:
- a plurality of pipelined execution units, at least one of the pipelined execution units comprising a multiplier circuit;
- the multiplier circuit comprising:
- a partial products generator capable of receiving a multiplicand value and a multiplier value and generating a plurality of partial products;
- a first summing array capable of summing a first subset of the partial products to produce a first summation value;
- and
- a second summing array capable of summing a second subset of the partial products to produce a second summation value;
- wherein at least one of:
- at least some of the partial products in the first subset are non-sequential ones of the plurality of partial products;
- and
- at least some of the partial products in the second subset are non-sequential ones of the plurality of partial products.
A method, comprising:
- generating a plurality of partial products using a multiplicand value and a multiplier value at a partial products generator;
- summing a first subset of the partial products to produce a first summation value;
- and
- summing a second subset of the partial products to produce a second summation value;
- wherein at least one of:
- at least some of the partial products in the first subset are non-sequential ones of the plurality of partial products;
- and
- at least some of the partial products in the second subset are non-sequential ones of the plurality of partial products.
A processor, comprising:
- at least one pipelined execution unit comprising a multiplier, the multiplier capable of:
- generating a plurality of partial products using a multiplicand value and a multiplier value;
- summing a first subset of the partial products to produce a first summation value;
- and
- summing a second subset of the partial products to produce a second summation value;
- wherein at least one of:
- at least some of the partial products in the first subset are non-sequential ones of the plurality of partial products;
- and
- at least some of the partial products in the second subset are non-sequential ones of the plurality of partial products.
Dependencies are inferred from the claim text.