Leading Zero Anticipatory (LZA) algorithm and logic for high speed arithmetic units

A circuit comprising:

• a plurality of logic elements to receive at least one bit of a first input mantissa and at least one bit of a second input mantissa;
• said plurality of logic elements to generate and transmit a predictive bit stream including an indicating bit in a bit position before a leading zero and before a leading one of the sum of said mantissas;
• a counter to generate and transmit a predictive count equal to a number of bits between a first bit generated of the predictive bit stream and said indicating one bit in the predictive bit stream;
• an adder circuit to receive said input mantissas and calculate a sum of said input mantissas;
• a shifter circuit to receive said sum from the adder circuit and said predictive count from the plurality of logic elements, arid to shift said sum to remove leading zeroes positioned in more significant positions than a most significant bit of the sum, wherein said shifting is performed a number of times equal to said predictive count;
• a compensatory shifter circuit to receive the shifted sum and to shift the sum to the left by zero to two bits to remove any remaining leading zeros.

A method of anticipating one of a number of leading zero and leading one bits in a sum of two numbers, the method comprising:

• receiving by a plurality of logic elements a plurality of groups of three bits from a first input mantissa and a plurality of groups of three bits from a second input mantissa, wherein the first groups of bits received are the most significant bits in the input mantissas, subsequent groups are received whose bits are less significant than the bits of the previously received bit groups by one bit position;
• generating a predictive bit stream by the plurality of logic elements possessing an indicating bit ma bit position before one of a leading zero and before a leading one of the sum of said mantissas, wherein the predictive bit stream has a one in a bit position if the addition of the corresponding group of three bits from first input mantissa and the corresponding group of three bits from second input mantissa produces a three bit sum in which a first two bits of the sum are one of 0 and 1 respectively and 1 and 0 respectively, and otherwise has a zero in that bit position;
• transmitting the predictive bit stream to a counter;
• and
• generating a predictive count by a counter equal to a number of bits between a first bit generated by the predictive bit stream and said indicating bit in the predictive bit stream.