Method of optimizing the timing between signals
AssigneeInfineon Technologies AG
InventorAaron John Nygren
Life of this patent
Estimating the term…
Abstract
A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according to which a delay test value of a clock delay line (CDL) are generated. According to the delay test values a clock signal (C) and a sample signal (S) are received through said clock delay line (CDL) and through said sample signal line (SSL), respectively. Respective phase differences for the distinct delay test values are obtained. A delay value is chosen and set for operation for which the respective obtained phase difference fits best to given target timing data.
Claims19
Method of optimizing the timing between signals to be latched and a respective latching clock signal with respect to a given circuitry arrangement,
- (a) receiving and providing target timing data (TTD), which are descriptive for a target timing between said signals to be latched and said latching clock signal,
- (b) receiving and providing test timings (TT), which are descriptive for test timings of said latching clock signal,
- (c) receiving and providing a test input signal (I), as a test signal to be latched,
- (d) for each of said test timings (TT):
- setting and receiving a delay test value of a clock delay line (CDL), describing the delay which is received by a clock signal traveling along said clock delay line (CDL),
- inputting and thereby receiving a clock signal (C) through said clock delay line (CDL) and said test input signal (I) as a sample signal (S) through a sample signal line (SSL) simultaneously and in particular at respective input sections thereof (CDLi, SSLi),
- measuring a phase difference between said clock signal (C) and said sample signal (S) at respective end sections or output sections (CDLo, SSLo) of said clock delay line (CDL) and of said sample signal line (SSL), respectively,
- (e) comparing the obtained phase differences to said target timing data (TTD), and
- (f) choosing and setting a distinct delay test value as a delay value for said clock delay line (CDL) for operating for which the respective phase difference fits best to the target timing data (TTD);
- wherein a non-feedback phase detection/phase alignment circuit (PD) is employed.
Method for latching received signals, comprising a process of adjusting the timing between said received signals to be latched and a latching clock signal, wherein said process of adjusting is carried out by:
- (a) receiving and providing target timing data (TTD), which are descriptive for a target timing between said signals to be latched and said latching clock signal,
- (b) receiving and providing test timings (TT), which are descriptive for test timings of said latching clock signal,
- (c) receiving and providing a test input signal (I), as a test signal to be latched,
- (d) for each of said test timings (TT):
- setting and receiving a delay test value of a clock delay line (CDL), describing the delay which is received by a clock signal traveling along said clock delay line (CDL),
- inputting and thereby receiving a clock signal (C) through said clock delay line (CDL) and said test input signal (I) as a sample signal (S) through a sample signal line (SSL) simultaneously and in particular at respective input sections thereof (CDLi, SSLi),
- measuring a phase difference between said clock signal (C) and said sample signal (S) at respective end sections or output sections (CDLo, SSLo) of said clock delay line (CDL) and of said sample signal line (SSL), respectively,
- (e) comparing the obtained phase differences to said target timing data (TTD), and
- (f) choosing and setting a distinct delay test value as a delay value for said clock delay line (CDL) for operation for which the respective phase difference fits best to the target timing data (TTD);
- wherein a non-feedback phase detecting/phase alignment circuit (PD) is employed.
Apparatus which is adapted and arranged for optimizing the timing between signals to be latched and a respective latching clock signal, the apparatus comprising:
- a signal input section though which input signals can be received;
- a clock signal input section;
- a plurality of latching lines coupled to the signal input section;
- a sample signal line coupled to the signal input section;
- a click delay line coupled to the clock input section, the clock delay line including a delay section;
- a phase detector coupled to the sample signal line and the clock delay line, wherein the phase detector comprises a non-feedback phase detecting/phase alignment circuit;
- a plurality of latches, each latch having a data input coupled to a respective one of the latching lines and each latch having a clock input coupled to the clock delay line.
Dependencies are inferred from the claim text.