Fractional-N frequency synthesizer with cascaded sigma-delta converters

A frequency synthesizer utilizing fractional-N synthesis, comprising:

• a phase detector having an input receivable of a reference frequency;
• a loop filter arranged to filter a control signal generated by the phase detector;
• a tunable oscillator arranged to receive the filtered control signal from said loop filter and provide an output frequency;
• an integer divider arranged to receive the output frequency of said oscillator, divide the output frequency by a division control number (N+F) and provide the divided output frequency to said phase detector, the division control number being made up of an integer (N) and a fraction portion (F) separated into at least two different fractions;
• a first sigma delta converter arranged to receive a first fractional value (F1) and output a first fraction (F1/P1);
• a first summer arranged to combine the first fraction (F1/P1) and a second fractional value (F2);
• a second sigma-delta converter arranged to receive the sum from said first summer (F2+F1/P1) and output a second fraction (F2/P2+F1/(P1 P2)) which constitutes the fraction portion of the division control number;
• and
• a second summer arranged to combine the fraction portion (F2/P2+F1/(P1 P2)) of the division control number and the integer (N) and output the sum to said integer divider (N+F2/P2+F1/(P1 P2));
• the first fraction being smaller than the second fraction and said first sigma-delta converter being driven at a lower clock rate than said second sigma-delta converter.

A frequency synthesizer utilizing fractional-N synthesis, comprising:

• a phase detector having an input receivable of a reference frequency;
• a loop filter arranged to filter a control signal generated by the phase detector;
• a tunable oscillator arranged to receive the filtered control signal from said loop filter and provide an output frequency;
• an integer divider arranged to receive the output frequency of said oscillator, divide the output frequency by a division control number (N+F) and provide the divided output frequency to said phase detector, the division control number being made up of an integer (N) and a fraction portion (F) separated into at least two different fractions;
• a first sigma delta converter arranged to receive a first fractional value (F1) and output a first fraction (F1/P1);
• a first summer arranged to combine the first fraction (F1/P1) and a second fractional value (F2);
• a second sigma-delta converter arranged to receive the sum from said first summer (F2+F1/P1) and output a second fraction (F2/P2+F1/(P1 P2));
• a second summer arranged to combine the second fraction (F2/P2+F1/(P1 P2)) and a third fractional value (F3);
• a third sigma-delta converter arranged to receive the sum from the second summer (F3+F2/P2+F1/(P1 P2)) and output a third fraction (F3/P3+F2/(P2 P3)+F1/(P1 P2 P3) which constitutes the fraction portion of the division control number;
• and
• a third summer arranged to combine the fraction portion (F3/P3+F2/(P2 P3)+F1/(P1 P2 P3) of the division control number and the integer (N) and output the sum to said integer divider (N+(F3/P3+F2/(P2 P3)+F1/(P1 P2 P3)));
• the first fraction being smaller than the second fraction, the second fraction being smaller than the third fraction and said first and second sigma-delta converters being driven at a lower clock rate than said third sigma-delta converter.

A method for synthesizing a frequency utilizing fractional-N synthesis, comprising the steps of:

• inputting a reference frequency to a phase detector;
• directing an output of the phase detector to a loop filter;
• directing an output from the loop filter to a tunable oscillator;
• directing an output frequency from the oscillator to an integer divider;
• inputting a division control number made up of an integer and a fraction portion separated into at least two different fractions into the integer divider;
• generating the fractions using at least two sigma-delta converters, each of the sigma delta converters processing a respective one of the at least two fractions;
• driving one of the sigma-delta converters processing a smaller fraction at a lower clock rate than one of the sigma-delta converters processing the largest fraction;
• dividing the output frequency from the oscillator by the division control number in the integer divider;
• and
• directing the output frequency from the integer divider to the phase detector.

A method for generating fractional values for input into sigma-delta converters designed to output an integer from −N to +M, comprising the steps of:

• dividing a desired output frequency by a reference frequency to obtain a division control number having an integer portion and a fraction portion;
• separating the fraction portion into a plurality of fractions;
• arranging the sigma-delta converters in a cascaded arrangement;
• providing a summer between each adjacent pair of cascaded sigma-delta converters and between the highest sigma-delta converter and an integer divider, each summer being arranged to receive an output from one of the sigma-delta converters and either the integer portion or one of the fractions;
• increasing the output from each sigma-delta converter by N;
• and
• subtracting N from the fractions or the integer portion being added by each summer and borrowing from a higher fraction or the integer portion when the fraction is less than N to thereby obtain modified fractions and a modified integer portion,
• whereby a result provided by each summer is greater than or equal to 0.