Frequency converter arrangement

#The invention relates to frequency converters. More particularly, the invention relates to a frequency converter arrangement with at least two successive heterodyne stages, a first heterodyne stage which converts an input signal with an adjustable first heterodyne frequency of a first superposition oscillator, and a second heterodyne stage which converts an input signal with a fixed second heterodyne frequency of a second superposition oscillator into a second intermediate frequency.

#Frequency arrangements of this type are known; see, e.g., German patent documents Nos. DE 27 44 432 and DE 40 21 294 and Japanese Patent Abstracts 60-28330A and 61-252720A. In such arrangements, a frequency divider which can be set in integral division ratios is used as frequency divider. The reference oscillator is an oscillator that is tuned to a fixed frequency. The phase comparison takes place at a frequency that is obtained by dividing the frequency of the reference oscillator. This frequency determines the step width with which the receive frequency can be shifted. To achieve a step width of 25 kHz, for example, just such a reference frequency is required. Due to this low reference frequency, the multiplication factor is large and the maximum possible control bandwidth is small, which leads to relatively bad phase noise and high transient recovery times in the frequency change. Thus, these known arrangements are not suitable for frequency conversion arrangements in receivers or spectrum analyzers with a frequency resolution in the Hz range.

#The state of the art in these devices involves the mixing of the first local oscillator with the harmonic of a good frequency reference and the synchronizing of the mixed signal with a synthesizer signal. Due to the independent synchronization of the first and second local oscillators, the phase noise of these two oscillators is added, whereby the first oscillator dominates, since it has the higher frequency and is tuned via a synthesizer. The difference of the phase noise between the highest receive frequency and a receive frequency near zero is approximately 6 dB, since the first local oscillator is typically tuned over an octave and the phase noise is determined by the multiplication factor to the reference. This is not sufficient for applications in the receive range of up to several GHz; a phase noise is expected which is proportional to the receive frequency.

#FIG. 1 illustrates the incorporation of principles of the invention in a spectrum analyzer.

#FIG. 2 illustrates the incorporation of principles of the invention in a signal generator.

#FIG. 1 depicts the application of the inventive principle in a spectrum analyzer, in which, subsequent to passing through a low-pass filter 11, an input frequency fe is converted into a fixed intermediate frequency ZF1 in a first mixer 3 with an adjustable first heterodyne frequency f1, which intermediate frequency ZF1 is converted into a lower second intermediate frequency ZF2 in a second mixer 4 with a fixed second heterodyne frequency f2, subsequent to passing through a bandpass filter 12. Corresponding concrete frequency values in the GHz range are illustrated in FIG. 1.

#The first heterodyne frequency f1 is generated in a first superposition oscillator 1; the second heterodyne frequency f2 is generated in a second superposition oscillator 2. The second superposition oscillator 2 is synchronized with a highly stable quartz frequency via a simple control loop. The first superposition oscillator 1 is synchronized with the frequency f5 of a synthesizer 7 via a phase control set, which synthesizer functions according to the known principle of direct digital synthesis (DDS) or fractional N-synthesis. In a mixer 5, the difference frequency f3 is formed from the two heterodyne frequencies f1 and f2 and is fed as divided frequency f4 to the phase detector 8 of the phase control loop for the oscillator 1 via an adjustable frequency divider 6. The frequency divider 6, which is adjustable with respect to a division ratio, is preferably a fractional N-frequency divider, the division ratio of which can be set by conversion to a fractional rational division ratio N.F, with N being the whole-number portion and F being a decimal portion. This fractional division ratio can be set as a digital value via an adjusting device 10. In addition, the synthesizer 7 can be set in its output frequency f5 via this setting means 10 in small increments of 1 Hz or less e.g. only 0.1 Hz. Via a control loop filter the output signal of the phase detector 8 synchronizes the first superposition oscillator 1 with the frequency f5, which is set at the synthesizer 7, which frequency is compared to the divided difference frequency f4 in the phase detector.

#The fractional N-divider has a resolution of 1/16, for example, and operates with single stage integration. Its division ratio is set such that the frequency f4 lies approximately in the frequency region in which the synthesizer 7 with its output frequency f5 can be set. In the illustrated exemplifying embodiment, the synthesizer can be adjusted in 0.1 Hz increments only in a narrow frequency range of 10 MHZ between 220 and 230 MHZ. The division factor N. F is selected as follows and set by the setting device 10: