Method and apparatus for jitter reduction in phase locked loops
AssigneeIntel Corporation
InventorsKeng L. Wong, Chee How Lim
Life of this patent
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AssigneeIntel Corporation
InventorsKeng L. Wong, Chee How Lim
Estimating the term…
A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.
A method for jitter reduction in a Phase Locked Loop (PLL) comprising:
A system comprising:
A microcircuit comprising:
Dependencies are inferred from the claim text.