Method and circuit for glitch-free changing of clocks having different phases

A circuit for glitch-free changing of clocks having different phases, wherein the circuit receives M clocks labeled by 1˜M and at least one data stream, in which the M clocks have the same frequency and are different in phase sequentially, and one of the M clocks (labeled by N, 1≦N≦M) is selected to be a system clock, the circuit comprising:

• a phase detector for receiving the data stream and the system clock, and generating a phase-up signal and a phase-down signal;
• a flag signal generator coupled to the phase detector for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein only one of the M flag signal is enabled at the same time;
• a select signal generator coupled to the flag signal generator, for receiving the M flag signals and the M clocks to correspondingly generate M select signals;
• enabling the select signal corresponding to the enabled flag signal;
• and
• an output stage coupled to the select signal generator, for receiving the M select signals and the M clocks, and then outputting the system clock, wherein the outputted system clock corresponds to one of the M clocks selected by the enabled select signal;
• wherein under the condition of clock N being at a first level, when the phase-up signal is enabled, the flag signal N+1 is enabled;
• and when the phase-down signal is enabled, the flag signal N−1 is enabled.

A method for changing clocks having different phase without glitch, used for receiving M clocks and at least one data stream and then outputting a system clock, wherein the M clocks have the same frequency but are different in phase sequentially, and one of the M clocks (labeled by clock N, 1≦N≦M) is currently the system clock, the method comprising the steps of:

• a. determining the phase of the data stream, and proceeding to a next step b if the phase of the data stream is changed, otherwise repeating step a;
• b. enabling a flag signal N+1 corresponding to the clock N+1 and then proceeding to a step c when the phase of the data stream lags behinds the phase of the system clock;
• c. enabling a flag signal N−1 corresponding to the clock N−1 and then proceeding to a step d when the phase of the data stream leads the phase of the system clock and the system clock is at a first level;
• d. enabling a select signal N+1 corresponding to the flag signal N+1 and then proceeding to a step f, when the clock N is at the first level;
• e. enabling a select signal N−1 in response to the flag signal N−1 and then proceeding to a step g, when the clock N is at the first level;
• f. setting the clock N+1 as the system clock and increasing N by one, and then returning to the step a;
• and
• g. setting the clock N−1 as the system clock and decreasing N by one, and then returning to the step a.