Back to results
US 7,023,865 B2Granted
Packet switch
AssigneeFujitsu Limited
InventorsNaoki Matsuoka, Hiroshi Tomonaga, Kenichi Kawarai, Masakatsu Nagata
Life of this patent
Estimating the term…
Abstract
A packet switch which can cyclically use α scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by α scheduler sections independently performing scheduling processes is disclosed.
Claims14
A packet switch, comprising:
- N input buffer sections, provided corresponding to N input lines, for storing a packet input through the corresponding input lines;
- α scheduler sections, connected to each of said N input buffer sections, for determining one of M output lines as a destination of the packet stored in each of said N input buffer sections by a scheduling process independently performed by each scheduler section, the time required by the scheduling process being longer than a shortest transmission interval of the packet;
- and
- a switch section, connected to each of said N input buffer section, for outputting the packet output from each of said N input buffer sections to the destination output line determined by said scheduler section,
- wherein results of scheduling processes by said α scheduler sections are cyclically used at a timing different with each other.
2 more elements
A packet switch, comprising:
- N input buffer sections, provided corresponding to N input lines, for storing a packet input through the corresponding input lines;
- α scheduler sections for determining one of M output lines as a destination of the packet stored in each of said N input buffer sections by a scheduling process independently performed by each scheduler section;
- and
- a switch section for outputting the packer output from each of said N input buffer sections to the destination output line determined by said scheduler section,
- wherein said N input buffer sections cyclically use results of scheduling processes by said α scheduler sections, and
- when a time required by said scheduler section to perform the scheduling process is L times as long as a shortest transmission interval of the packet, the number α of scheduler sections is set to a value equal to or larger than the multiple L.
3 more elements
A packet switch, comprising:
- N input buffer sections, provided corresponding to N input lines, for storing a packet input through the corresponding input lines;
- α scheduler sections for determining one of M output lines as a destination of the packer stored in each of said N input buffer sections by a scheduling process independently performed by each scheduler section;
- and
- a switch section for outputting the packet output from each of said N input buffer sections to the destination output line determined by said scheduler section,
- wherein said N input buffer sections cyclically use results of scheduling processes by said α scheduler section, and
- said scheduler section performs the scheduling process including an unused line, and performs a re-reading process among the actually used input and output lines and the unused lines, thereby obtaining a plurality of scheduling process results by performing one scheduling process.
3 more elements
Dependencies are inferred from the claim text.