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US 7,023,761 B1Granted
Programmable stackable memory array system
AssigneeTexas Instruments Incorporated
InventorHiep V. Tran
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system. The memory array system comprises a plurality of memory cells and a programmable switching control circuit. The programmable switching control circuit is operative to arrange the plurality of memory cells in a standard configuration in an activation mode and to arrange the plurality of memory cells in a stacked configuration in a retention mode.
Claims20
A memory array system comprising:
- a plurality of memory cells;
- and
- a programmable switching control circuit operative to arrange the plurality of memory cells in a standard configuration in an activation mode and to arrange the plurality of memory cells in a stacked configuration in a retention mode.
A memory array system comprising:
- a first plurality of memory cells interconnected between a positive voltage rail and a node;
- and
- a second plurality of memory cells interconnected between the node and a negative voltage rail, the node being set at a node voltage potential that is based on a ratio of a quantity of memory cells in the first plurality of memory cells relative to a quantity of memory cells in the second plurality of memory cells.
A mobile communication device comprising:
- an antenna for transmitting and receiving wireless signals;
- a transceiver;
- and
- a memory array system comprising a plurality of memory cells that are switchable between a standard configuration and a stacked configuration.
1 more element
Dependencies are inferred from the claim text.