Memory arrangement for processing data, and method
AssigneeInfineon Technologies AG
InventorFrank Hellwig
Life of this patent
Estimating the term…
Abstract
The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.
Claims20
Memory arrangement for processing data, having:
- (a) an external memory, for writing and reading data,
- (b) an interface which is coupled to the memory and, during an access operation, has data together with a control signal indicating that valid data are being applied to the interface,
- (c) a register device whose data input is connected to the interface for the purpose of inputting the data applied thereto and which has a clock input for inputting a delayed clock signal,
- (d) a DLL circuit which has a control input for inputting the control signal, with a change in the control signal activating the DLL circuit, and which has a clock output for providing delayed clock signal which stipulates the sampling time in the register device and which synchronizes the register device, and
- (e) a device which effects forced access to the memory after a predetermined length of time within which there has been no access to the memory.
Dependencies are inferred from the claim text.