Low power manager for standby operation of a memory system
AssigneeInternational Business Machines Corporation
InventorsDavid R. Hanson, Gregory J Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
Claims20
A memory system including:
- a memory array,
- a wordline driver circuit for said memory array having wordlines connected to said memory array;
- a standby power management (SPM) circuit having a power down (WLPWRDN) input for receiving a power down input signal;
- said SPM circuit switching between providing a normal output on a power down (WLPDN) output line to said wordline driver circuit during normal operation and replacing said normal output with a standby output on said WLPDN output line to said wordline driver circuit in response to receipt of a said power down input signal on said WLPWRDN input;
- whereby said standby power management circuit reduces power consumption by said memory array in the presence of a said standby output.
A memory system including:
- a memory array;
- a wordline driver for said memory array;
- a standby power management (SPM) circuit including an input terminal for receiving a power down (WLPWRDN) signal and an output terminal connected to driver circuits in said wordline driver, and
- said output terminal is connected to vary bias to said driver circuits in said wordline driver to vary operation thereof between full power current operation and reduced standby current operation in response to said power down (WLPWRDN) signal at said input terminal of said SPM circuit;
- whereby said standby power management circuit reduces power consumption by said memory array during standby operation.
Dependencies are inferred from the claim text.