DRAM power bus control
AssigneeMicron Technology, Inc.
InventorGeorge B. Raad
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.
Claims20
A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said chip further having non-dynamic random access memory circuits, said method comprising:
- powering at least some said non-dynamic random access memory circuits with a first power bus;
- powering reads and writes of said array with a second power bus, said second power bus not coupled to said first power bus;
- and
- coupling said second power bus to a third power bus for a finite period of time during said periodic refreshing of said array.
Apparatus for controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said chip further having non-dynamic random access memory circuits, said apparatus comprising:
- means for powering at least some said non-dynamic random access memory circuits;
- means for powering reads and writes of said array, said means for powering reads and writes different from said means for powering at least some said non-dynamic random access memory circuits;
- and
- means for increasing power of said means for powering reads and writes for a finite period of time during said periodic refreshing of said array.
A method for controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said chip further having non-dynamic random access memory circuits, said method comprising:
- powering at least some said non-dynamic random access memory circuits with a first voltage;
- powering reads and writes of said array with a second voltage;
- and
- powering reads and writes for a finite period of time during said periodic refreshing of said array with a third voltage, wherein said third voltage is higher than said second voltage.
Dependencies are inferred from the claim text.