Low power control circuit and method for a memory device

A low power control circuit for transitioning a memory device from a first operating mode to a low power operating mode when a first control signal has a first value, and transitioning the memory device from the low power operating mode to the first operating mode when the first control signal has a second value, said low power control circuit comprising:

• a differential amplifier connected to a reference voltage and a first control signal;
• a buffer circuit having an input connected to the first control signal;
• and
• a first logic circuit connected to said differential amplifier and said buffer circuit, wherein in the first operating mode said first logic circuit disables the buffer circuit and enables the differential amplifier such that the differential amplifier is used to detect the first value, and in the low power mode, enables the buffer circuit and disables the differential amplifier until the buffer circuit detects the second value,
• wherein said memory device is transitioned to said first operating mode only after both said buffer circuit and said differential amplifier detect the second value, and wherein said low power control circuit is adapted to ignore the reference voltage during the low power operating mode.

A memory device comprising:

• a low power control circuit for transitioning said memory device between a first operating mode and a low power operating mode, said low power control circuit comprising:
• a differential circuit connected to a reference voltage and a first control signal;
• and
• a buffer circuit having an input connected to the first control signal;
• wherein in the first operating mode said differential circuit is used to detect a first value of the first control signal and causes a transition from the first operating mode to the low power operating mode, and in the low power operating mode said buffer circuit and said differential circuit are used to detect a second value of the first control signal and cause a transition from the low power operating mode to the first operating mode, and wherein a level of the reference voltage is altered during the low power operating mode.

A memory device comprising:

• a low power control circuit for transitioning said memory device from a first operating mode to a low power operating mode when a first control signal has a first value, and transitioning the memory device from the low power operating mode to the first operating mode when the first control signal has a second value, said low power control circuit comprising:
• a differential amplifier connected to a reference voltage and a first control signal;
• a buffer circuit having an input connected to the first control signal;
• and
• a first logic circuit connected to said differential amplifier and said buffer circuit, wherein in the first operating mode said first logic circuit disables the buffer circuit and enables the differential amplifier such that the differential amplifier is used to detect the first value, and in the low power mode, enables the buffer circuit and disables the differential amplifier until the buffer circuit detects the second value,
• wherein said memory device is transitioned to said first operating mode only after both said buffer circuit and said differential amplifier detect the second value, and wherein said low power control circuit is adapted to ignore the reference voltage during the low power operating mode.

A processor system comprising:

• a processor;
• and
• a memory device comprising a low power control circuit for transitioning said memory device between a first operating mode and a low power operating mode, said low power control circuit comprising:
• a differential circuit connected to a reference voltage and a first control signal, and
• a buffer circuit having an input connected to the first control signal,
• wherein in the first operating mode said differential circuit is used to detect a first value of the first control signal and causes a transition from the first operating mode to the low power operating mode, and in the low power operating mode said buffer circuit and said differential circuit are used to detect a second value of the first control signal and cause a transition from the low power operating mode to the first operating mode,
• wherein the reference voltage is floated during the low power operating mode.

A processor system comprising:

• a processor;
• and
• a memory device comprising a low power control circuit for transitioning said memory device between a first operating mode and a low power operating mode, said low power control circuit comprising:
• a differential circuit connected to a reference voltage and a first control signal, and
• a buffer circuit having an input connected to the first control signal,
• wherein in the first operating mode said differential circuit is used to detect a first value of the first control signal and causes a transition from the first operating mode to the low power operating mode, and in the low power operating mode said buffer circuit and said differential circuit are used to detect a second value of the first control signal and cause a transition from the low power operating mode to the first operating mode, wherein the reference voltage is grounded during the low power operating mode.

A processor system comprising:

• a processor;
• and
• a memory device comprising a low power control circuit for transitioning said memory device between a first operating mode and a low power operating mode, said low power control circuit comprising:
• a differential circuit connected to a reference voltage and a first control signal, and
• a buffer circuit having an input connected to the first control signal,
• wherein in the first operating mode said differential circuit is used to detect a first value of the first control signal and causes a transition from the first operating mode to the low power operating mode, and in the low power operating mode said buffer circuit and said differential circuit are used to detect a second value of the first control signal and cause a transition from the low power operating mode to the first operating mode,
• wherein a current reduced by about twenty-five percent of full current is applied to said differential circuit when disabled.

A processor system comprising:

• a processor;
• and
• a memory device comprising a low power control circuit for transitioning said memory device between a first operating mode and a low power operating mode, said low power control circuit comprising:
• a differential circuit connected to a reference voltage and a first control signal, and
• a buffer circuit having an input connected to the first control signal,
• wherein in the first operating mode said differential circuit is used to detect a first value of the first control signal and causes a transition from the first operating mode to the low power operating mode, and in the low power operating mode said buffer circuit and said differential circuit are used to detect a second value of the first control signal and cause a transition from the low power operating mode to the first operating mode,
• wherein a current reduced by about seventy-five percent of full current is applied to said differential circuit when disabled.

A processor system comprising:

• a processor;
• and
• a memory device including a low power control circuit for transitioning said memory device from a first operating mode to a low power operating mode when a first control signal has a first value, and transitioning the memory device from the low power operating mode to the first operating mode when the first control signal has a second value, said low power control circuit comprising:
• a differential amplifier connected to a reference voltage and a first control signal,
• a buffer circuit having an input connected to the first control signal, and
• a first logic circuit connected to said differential amplifier and said buffer circuit, wherein in the first operating mode said first logic circuit disables the buffer circuit and enables the differential amplifier such that the differential amplifier is used to detect the first value, and in the low power mode, enables the buffer circuit and disables the differential amplifier until the buffer circuit detects the second value,
• wherein said memory device is transitioned to said first operating mode only after both said buffer circuit and said differential amplifier detect the second value, and wherein said low power control circuit is adapted to ignore the reference voltage during the low power operating mode.

A method of transitioning a memory device between a first operating mode and a low power operating mode, said method comprising:

• detecting, using a differential circuit, when a first control signal has a first value;
• transitioning the memory device from the first operating mode to the low power operating mode;
• disabling the differential circuit;
• changing a level of a reference voltage used by the differential circuit;
• enabling a buffer circuit;
• detecting, at the buffer circuit, when the first control signal has a second value;
• restoring the level of the reference voltage;
• enabling the differential circuit;
• detecting, at the buffer circuit and the differential circuit, when the first control signal has the second value;
• and
• transitioning the memory device from the low power operating mode to the first operating mode.

A method of transitioning a memory device between a first operating mode and a low power operating mode, said method comprising:

• comparing a first control signal to a reference voltage;
• determining whether the first control signal has a first value based on the comparison;
• transitioning the memory device from the first operating mode to the low power operating mode if the first control signal has the first value;
• determining when the first control signal has a second value;
• ensuring that the first control signal has the second value;
• and
• transitioning the memory device from the low power operating mode to the first operating mode if it is ensured that the first control signal has the second value,
• wherein a level of the reference voltage is altered during the low power operating mode.