Semiconductor device having standby mode and active mode
AssigneesRenesas Technology Corp., Mitsubishi Electric Engineering Company Limited
InventorsMihoko Akiyama, Fukashi Morishita
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Abstract
An internal potential generation circuit of an SDRAM includes a standby VDDS generation circuit which has a relatively low current driving force and which generates an internal power supply potential, and an active VDDS generation circuit which has a relatively high current driving force, which is activated during a period after an external power supply potential is applied until a negative potential reaches a threshold potential, and in an activation period, and which generates the internal power supply potential. Therefore, it is possible to raise the internal power supply potential stably without increasing standby current when the power supply is turned on.
Claims10
A semiconductor device having a standby mode and an active mode, comprising:
- a first internal power supply potential generation circuit having a first current driving force, and driven by an external power supply potential to generate an internal power supply potential not exceeding the external power supply potential;
- a second internal power supply potential generation circuit having a second current driving, force higher than the first current driving force, activated in a period when the external power supply potential is applied and in an active mode, driven by the external power supply potential, and generating the internal power supply potential;
- an internal circuit driven by the internal power supply potential;
- an internal potential generation circuit driven by the external power supply potential, and generating an internal potential;
- and
- an internal potential detection circuit setting a detection signal to an active level when the external power supply potential is applied, and setting the detection signal to an inactive level when the internal potential reaches a first potential, wherein, in the period, the detection signal is at the active level.
A semiconductor device having a standby mode and an active mode, comprising:
- a first internal power supply potential generation circuit having a first current driving force, and driven by an external power supply potential to generate an internal power supply potential not exceeding the external power supply potential;
- a second internal power supply potential generation circuit having a second current driving force, higher than the first current driving force, activated in a period when the external power supply potential is applied and in an active mode, driven by the external power supply potential, and generating the internal power supply potential;
- an internal circuit driven by the internal power supply potential;
- an internal potential generation circuit driven by the external power supply potential, and generating an internal potential;
- an internal potential detection circuit setting a detection signal to an active level when the external power supply potential is applied, and setting the detection signal to an inactive level when the internal potential reaches a first potential;
- a first signal generation circuit setting a power-on reset signal at the active level when the external power supply potential is applied, and setting the power-on reset signal to an inactive level when the external power supply potential reaches a second potential;
- and
- a second signal generation circuit setting a control signal to an active level when the power-on reset signal is at the inactive level, and setting the control signal to an inactive level when the detection signal is at the inactive level, wherein, in the period, the control signal is at the active level.
A semiconductor device having a standby mode and an active mode, comprising:
- a first internal power supply potential generation circuit having a first current driving force, and driven by an external power supply potential to generate an internal power supply potential not exceeding the external power supply potential;
- a second internal power supply potential generation circuit having a second current driving force, higher than the first current driving force, activated in a period when the external power supply potential is applied and in an active mode, driven by the external power supply potential and generating the internal power supply potential;
- an internal circuit driven by the internal power supply potential;
- a first internal potential generation circuit driven by the internal power supply potential, and generating a first internal potential;
- a second internal potential generation circuit driven by the internal power supply potential, and generating a second internal potential;
- and
- an internal potential detection circuit setting a detection signal to an active level when the external power supply potential is applied, and setting the detection signal to an inactive level when both the first and second internal potentials reach a reference potential, wherein, in the period, the detection signal is at the active level.
Dependencies are inferred from the claim text.