Semiconductor memory device and address conversion circuit

Abstract

It is an object of the present invention to provide a semiconductor memory device with a suitable redundancy circuit and an address conversion circuit, wherein external addresses are allocated to both a memory cell array which needs refresh, typically DRAM and another memory cell array which does not need refresh, typically SRAM. The semiconductor memory device comprises a dynamic memory cell array 11 further comprising an array of a plurality of dynamic memory cells, a static memory cell array 12 further comprising an array of a plurality of static memory cells, a pre-decoder 101 for converting an external address Add into a row pre-decode signal A1 or A2 which corresponds to any memory cell in the dynamic memory cell array 11 or the static memory cell array 12, a redundancy program circuit 103 for specifying a memory cell being to be replaced in the dynamic memory cell array 11, and a second conversion means (redundancy judging circuit) for converting an external address Add, which corresponds to the memory cell specified by the redundancy program circuit 103, into a row pre-decode signal A4, which corresponds to a predetermined memory cell in the static memory cell array 12.

Dependencies are inferred from the claim text.