Reconfigurable SRAM-ROM cell

A memory array comprising:

• a bitline;
• and
• a plurality of memory cells, each of the plurality of memory cells having:
• a configuration bit terminal;
• a pair of cross-coupled inverters having first and second bit nodes, wherein one of the first and second bit nodes is connected to the configuration bit terminal;
• an access transistor having a first current-carrying terminal connected to the bitline, a second current-carrying terminal connected to the first bit node, and an access-transistor control terminal;
• and
• a memory transistor having a first current-carrying terminal connected to one of the first and second bit nodes, a second current-carrying terminal connected to a one of first and second power supply nodes nodes, and a memory-transistor control terminal;
• wherein each of the plurality of memory cells further includes a programmable interconnection interposed between the second current-carrying terminal of the memory transistor and the first and second power supply nodes.

A circuit comprising:

• a plurality of memory cells, each memory cell supporting a random-access memory mode and a read-only memory mode;
• and
• an array of configurable logic resources connected to the memory cells;
• wherein each memory cell includes a mode switch selecting one of the random-access memory mode or the read-only memory mode;
• and
• wherein each memory cell further includes a configuration bit terminal, each configuration bit terminal coupled to at least one configurable logic resource in the array of configurable logic resources.

A programmable logic device comprising:

• configurable logic resources having a plurality of configuration bit terminals;
• and
• a plurality of memory cells, each memory cell including:
• a configuration bit node connected to one of the plurality of configuration bit terminals of the configurable logic resources and providing a configuration-bit signal;
• a random-access memory element;
• a read-only memory element;
• and
• at least one memory control terminal selecting one of the random-access memory element and the read-only memory element to control the configuration-bit signal.