Semiconductor integrated circuit adapted to output pass/fail results of internal operations
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Claims19
A semiconductor integrated circuit comprising:
- an internal circuit configured to execute a first operation and a second operation concurrently;
- and
- an output circuit connected to the internal circuit, the output circuit configured to output to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
A semiconductor integrated circuit comprising:
- a plurality of data cache circuits connected to data input/output lines, the plurality of data cache circuits configured to hold data temporarily;
- and
- a plurality of sense latch circuits connected to the plurality of data cache circuits, the plurality of sense latch circuit configured to sense and latch data read from memory cells and latching data to be programmed into memory cells,
- wherein the data cache circuits are provided in the same number as the sense latch circuits.
A semiconductor integrated circuit comprising:
- a plurality of data cache circuits connected to data input/output lines, the plurality of data cache circuits configured to hold data temporarily;
- and
- a plurality of sense latch circuits connected to the plurality of data cache circuits and bit lines, the plurality of sense latch circuit configured to sense and latch data read from memory cells and latching data to be programmed into memory cells,
- wherein the data cache circuits are provided in the same number as the sense latch circuits, and
- the data cache circuits are provided in half of the number of the bit lines, and the sense latch circuits are provided in half the number of the bit lines.
The A semiconductor integrated circuit comprising:
- a plurality of data cache circuits connected to data input/output lines, the plurality of data cache circuits configured to hold data temporarily;
- and
- a plurality of sense latch circuits connected to the plurality of data cache circuits and bit lines, the plurality of sense latch circuit configured to sense and latch data read from memory cells and latching data to be programmed into memory cells,
- wherein the cache circuits are provided in half of the number of bit lines, and sense latch circuits are provided in half of number of the bit lines.
An operating method of a semiconductor integrated circuit executing a first operation and a second operation concurrently, comprising:
- outputting to the outside of the semiconductor integrated circuit first information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Dependencies are inferred from the claim text.