Non-volatile memory and method with improved sensing

In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:

• a controller;
• and
• a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit further comprising:
• a discriminator coupled to receive a conduction current of an associated memory cell, said discriminator discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
• a latch being set to register the associated memory cell in response to said discriminator identifying a conduction current higher than said predetermined demarcation current value;
• an inhibitor to turn off the conduction current of the associated memory cell;
• an inhibitor enabler responsive to said plurality of sensing circuits having their discriminators completed their identifications and said latch being set;
• and wherein
• said controller controls said plurality of sensing circuits to operate a predetermined number of times before reading out the determined memory state.

In a non-volatile memory device having a plurality of memory cells to be sensed in parallel, each memory cell having a source electrode, and the plurality of memory cells having their source electrodes coupled together into a combined source line, a read system comprising:

• a controlling means;
• and
• a plurality of sensing circuits for sensing conduction currents of said plurality of memory cells in parallel, each sensing circuit further comprising:
• means for discriminating whether the conduction current is higher or lower than a predetermined demarcation current value;
• means for registering the associated memory cell in response whenever its conduction current is identified to be higher than said predetermined demarcation current value;
• inhibitor means for inhibiting the conduction current of the associated memory cell;
• means for enabling said inhibitor means responsive to said plurality of sensing circuits having their discriminators completed their identifications and said latch being set;
• and wherein and
• means for inhibiting the associated memory cell with said higher conduction current;
• and wherein
• said controlling means operating said plurality of sensing circuits a predetermined number of times before reading out the sensed memory state in a final pass.

A non-volatile memory, comprising:

• an array of memory storage units;
• a plurality of sense amplifiers for sensing a group of memory storage units in parallel;
• each of said plurality of sense amplifiers having predetermined properties dependent on a set common parameters and a set of control signals;
• and
• a reference circuit sharing a common environment with said plurality of sense amplifier, said reference circuit for calibrating said set of common parameters with respect to the common environment and generating said set of control signals accordingly so that said plurality of sense amplifiers are controlled to have its predetermined properties enforced.