Overerase correction in flash EEPROM memory

A semiconductor device comprising a memory array including a plurality of memory cells disposed in a plurality of bit lines, said semiconductor device comprising circuitry for overerase correction of said memory cells after the memory cells have been erased, said circuitry comprising:

• (a) means for setting a gate voltage of memory cells from a first selected bit line that exhibits leakage current above a threshold value to an initial voltage level;
• (b) means for applying a series of overerase correction pulses to said first selected bit line during a selected time period;
• (c) means for detecting during said selected time period whether said bit line exhibits leakage current above said threshold value;
• (d) means for, if said bit line exhibits leakage current above said threshold value after said selected time period, increasing said gate voltage and repeating the functions of means (b) and (c);
• and
• (e) means for, if it is detected that said bit line does not exhibit leakage current above said threshold value during said selected time period, selecting a second bit line and repeating the functions of means (a) through (d).

A method of overerase correction for memory cells in a flash memory array after the memory cells have been erased, comprising the following steps:

• (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level, said initial voltage level being a negative voltage;
• (b) applying a series of overerase correction pulses to said first selected bit line during a selected time period;
• (c) detecting during said selected time period after each overerase correction pulse from said series of correction pulses whether said bit line exhibits leakage current above said threshold value;
• (d) if said bit line exhibits leakage current above said threshold value after said selected time period, incrementing said gate voltage to a second voltage level and repeating steps (b) and (c);
• and
• (e) if it is detected that said bit line does not exhibit leakage current above said threshold value during said selected time period, selecting a second bit line and repeating steps (a) through (d).

A semiconductor device comprising a memory array including a plurality of memory cells disposed in a plurality of bit lines, said semiconductor device comprising circuitry for overerase correction of said memory cells after the memory cells have been erased, said circuitry comprising:

• a source of overerase correction pulses to be applied during a selected time period;
• an overerase verify circuit, said verify circuit detecting whether a selected bit line exhibits leakage current above a threshold value during said selected time period;
• a gate voltage source, said gate voltage source responsive to a control signal representing a gate voltage from a plurality of gate voltages to be applied to said memory cells from said selected bit line during application of said overerase correction pulses;
• and
• a bit line selection circuit, said bit line selection circuit responsive to a control signal indicating if it has been detected during said selected time period if said selected bit line exhibits leakage current above said threshold value.

A method of overerase correction for memory cells in a memory array after the memory cells have been erased, comprising the following steps:

• (a) setting a gate voltage of memory cells from a first selected bit line including an overerased memory cell to an initial voltage level;
• (b) applying a series of overerase correction pulses to said first selected bit line during a selected time period;
• (c) detecting during said selected time period whether said bit line includes an overerased memory cell;
• (d) if said bit line includes an overerased memory cell after said selected time period, increasing said gate voltage and repeating steps (b) and (c);
• and
• (e) if it is detected that said bit line does not include an overerased memory cell during said selected time period, selecting a second bit line and repeating steps (a) through (d).