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AssigneeSony Corporation
InventorsShunji Sekimoto, Tomohiro Namise
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The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
A data erasing method for erasing stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate, said data erasing method comprising:
A data erasing method for erasing stored data by applying an erasing voltage between a well provided at a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate, said data erasing method comprising:
A memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate, wherein;
A memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a well provided at a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate, wherein;
Dependencies are inferred from the claim text.