US 7,023,728 B2Granted

Semiconductor memory system including selection transistors

AssigneeSTMicroelectronics S.r.l.

InventorLuigi Pascucci

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Abstract

A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively. Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively. The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

Claims29

Dependent claims

Semiconductor memory system comprising:

a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively,
a plurality of conduction lines which can be selectively connected to the plurality of column lines and including a first and a second conduction line which can be connected to said first and second column lines,
generating means provided with a plurality of output lines including at least a first and a second output line to make available a first and a second reading/writing voltage respectively to be supplied to said first and second terminal,
groups of selection transistors which can be activated/deactivated to/from conduction by means of command lines to selectively connect the plurality of output lines to the plurality of conduction lines,
wherein each group of transistors comprises at least a first and a second transistor connected to the same command line, said first and second transistors having corresponding operative terminals connected directly to the first and to the second output lines respectively, and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

2 more elements

Dependencies are inferred from the claim text.