Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsKiyoo Itoh, Kazuo Nakazato
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.
Claims6
A semiconductor integrated circuit device comprising:
- a plurality of first read data lines;
- a plurality of second read data lines;
- a plurality of first write data lines;
- a plurality of second write data lines;
- a plurality of first memory cells, each including a first storage transistor whose source and drain are coupled between a first potential and corresponding one of the first read data lines, and a first write transistor whose source and drain are coupled between a gate of the first storage transistor and corresponding one of the plurality of first write data lines;
- a plurality of second memory cells, each including a second storage transistor whose source and drain are coupled between the first potential and corresponding one of the plurality of second read data lines, and a second write transistor whose source and drain are coupled between a gate of the second storage transistor and corresponding one of the plurality of second write data lines;
- a pair of common data lines, one of the pair of common data lines being coupled to the plurality of first read data lines and the plurality of first write data lines via the plurality of first switches, and the other of the pair of common data lines being coupled to the plurality of second read data lines and the plurality of second write data lines via a plurality of second switches;
- and
- a sense amplifier coupled to the pair of common data lines.
Dependencies are inferred from the claim text.