Transferring a digital video stream through a series of hardware modules

A system comprising:

• an input port configured to receive an input stream of video data words and a synchronous clock signal C0;
• a first buffer coupled to receive another clock signal K0 and to generate a local clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, is coupled to receive the local clock signal, and configured to buffer the local clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=1, 2, . . . , NR−1 includes a link interface buffer coupled to receive the stream SK−1 of video data words and the synchronous clock SC(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K), wherein the stream S−1 is the input stream and the synchronous clock SC(−1) is the synchronous clock C0.

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers coupled in a linear series, wherein each video router receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock;
• wherein each video router includes an output interface configured to transmit a stream of video data words onto a connecting bus, wherein the output interface transmits one video data word of the stream onto the connecting bus in response to each triggering edge of the output clock, wherein the output interface buffers the output clock to generate a synchronous clock and transmits the synchronous clock onto the connecting bus, wherein at least a subset of the connecting buses conducts its respective stream and synchronous clock to a next video router;
• wherein each video router includes a link interface buffer configured to receive a respective stream of video data words and a respective synchronous clock from a respective connecting bus, wherein the link interface buffer is configured to receive and internally store one of the video data words of the received stream in response to each triggering edge of the received synchronous clock, wherein the link interface buffer is configured to generate a local stream by accessing one of the internally stored video data words in response to each triggering edge of the output clock.

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=0, 1, 2, . . . , NR−1 includes a link interface buffer configured to receive the stream SK−1 of video data words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K);
• wherein each video router VR(K) for K=1, 2, . . . , NR−1 further includes a modification unit, wherein the modification unit is configured to receive the local stream LS(K) of video data words and to modify the local stream LS(K) to generate a modified stream MS(K) of video data words, wherein the output interface is configured to pass one video data word of the modified stream MS(K) onto the connecting bus CS(K), in response to each triggering edge of the output clock OC(K), to generate the stream SK;
• wherein each video router VR(K), K=0, 1, 2, . . . , NR−1 further includes a horizontal counter, a vertical counter, and a set of horizontal boundary registers and a set of vertical boundary registers, wherein the video router VR(K) receives a stream PX(K) of pixels corresponding to a Kth region of a video frame or video field;
• and
• wherein the vertical counter in each video router VR(K), K=1, 2, . . . , NR−1, is coupled to receive a vertical reset field of each video data word of the local stream LS(K), wherein the vertical counter is configured to reset in response to a reset event occurring in the vertical reset field.

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=1, 2, . . . , NR−1 includes a link interface buffer configured to receive the stream SK−1 of video data words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K)
• wherein each video router VR(K) for K=1, 2, . . . , NR−1 further includes a modification unit, wherein the modification unit is configured to receive the local stream LS(K) of video data words and to modify the local stream LS(K) to generate a modified stream MS(K) of video data words, wherein the output interface is configured to pass one video data word of the modified stream MS(K) onto the connecting bus CS(K), in response to each triggering edge of the output clock OC(K), to generate the stream SK;
• wherein each video router VR(K), K=0, 1, 2, . . . , NR−1 further includes a horizontal counter, a vertical counter, and a set of horizontal boundary registers and a set of vertical boundary registers, wherein the video router VR(K) receives a stream PX(K) of pixels corresponding to a Kth region of a video frame or video field;
• and
• wherein the video router VR(0) is configured to embed a reset event in a horizontal reset field of a video data word of the stream S0, prior to transmission from the corresponding output interface, in response to the horizontal counter of the video router VR(0) attaining a beginning of line condition.

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=1, 2, . . . , NR−1 includes a link interface buffer configured to receive the stream SK−1 of video data words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K)
• wherein each video router VR(K) for K=1, 2, . . . , NR−1 further includes a modification unit, wherein the modification unit is configured to receive the local stream LS(K) of video data words and to modify the local stream LS(K) to generate a modified stream MS(K) of video data words, wherein the output interface is configured to pass one video data word of the modified stream MS(K) onto the connecting bus CS(K), in response to each triggering edge of the output clock OC(K), to generate the stream SK;
• wherein each video router VR(K), K=0, 1, 2, . . . , NR−1 further includes a horizontal counter, a vertical counter, and a set of horizontal boundary registers and a set of vertical boundary registers, wherein the video router VR(K) receives a stream PX(K) of pixels corresponding to a Kth region of a video frame or video field;
• and
• wherein the video router VR(0) is configured to embed a reset event in a vertical reset field of a video data word of the stream S0, prior to transmission from the corresponding output interface, in response to the vertical counter of the video router VR(0) attaining a beginning of frame condition.

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=1, 2, . . . , NR−1 includes a link interface buffer configured to receive the stream SK−1 of video data words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K);
• wherein the link interface buffer in each video router VR(K), K=1, 2, . . . , NR−1, comprises a read pointer counter, a write pointer counter, and a memory, wherein the write counter increments a write pointer in response to triggering edges of the synchronous clock SC(K−1), wherein the read counter increments a read pointer in response to triggering edges of the output clock OC(K), wherein the write pointer determines write locations in the memory for storing received video data words of the stream SK−1, wherein the read pointer determines read locations in the memory for reading video data words from the memory;
• and
• wherein the first reset signal is synchronized with the output clock OC(K).

A system comprising:

• a clock generator configured to generate a source clock signal;
• a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series, wherein the number of video routers NR is greater than or equal to two, wherein each video router VR(K), K=0, 1, . . . , NR−1, receives the source clock signal from the clock generator, and buffers the source clock signal to generate an output clock OC(K);
• wherein each video router VR(K), K=0, 1, . . . , NR−1 includes an output interface configured to transmit a stream SK of video data words onto a connecting bus CB(K), wherein the output interface transmits one video data word of the stream SK onto the connecting bus CB(K) in response to each triggering edge of the output clock OC(K), wherein the output interface buffers the output clock OC(K) to generate a synchronous clock SC(K) and transmits the synchronous clock SC(K) onto the connecting bus CB(K), wherein, for K=0, 1, . . . , NR−2, the connecting bus CB(K) conducts the stream SK and the synchronous clock SC(K) to the next video router VR(K+1);
• wherein each video router VR(K), K=1, 2, . . . , NR−1 includes a link interface buffer configured to receive the stream SK−1 of video data words and the synchronous clock SC(K−1) from the connecting bus CB(K−1), wherein the link interface buffer is configured to receive and internally store one of the video data words of the stream SK−1 in response to each triggering edge of the synchronous clock SC(K−1), wherein the link interface buffer is configured to generate a local stream LS(K) by accessing one of the internally stored video data words in response to each triggering edge of the output clock OC(K);
• wherein the link interface buffer in each video router VR(K), K=1, 2, . . . , NR−1, comprises a read pointer counter, a write pointer counter, and a memory, wherein the write counter increments a write pointer in response to triggering edges of the synchronous clock SC(K−1), wherein the read counter increments a read pointer in response to triggering edges of the output clock OC(K), wherein the write pointer determines write locations in the memory for storing received video data words of the stream SK−1, wherein the read pointer determines read locations in the memory for reading video data words from the memory;
• and
• wherein the link interface buffer in each video router VR(K), K=1, 2, . . . , NR−1, also includes a synchronization circuit configured to receive a first reset signal and to generate a second reset signal synchronized with the synchronous clock SC(K−1), wherein the read pointer counter is coupled to receive the first reset signal, wherein the write pointer counter is coupled to receive the second reset signal.