US 7,023,415 B2Granted

Shift register, data-line driving circuit, and scan-line driving circuit

AssigneeSeiko Epson Corporation

InventorsShin Fujita, Shinsuke Fujikawa

Life of this patent

Estimating the term…

Abstract

The invention provides a shift register that reliably operates even when the driving ability of a clock signal is low. A data-line driving circuit includes a shift-register section, which has serially-connected shift-register unit circuits Ua1 to Uan+2, and a clock-signal control section, which has serially-connected control unit circuits Uc1 to Ucn+2. Each control unit circuit Uc1 to Ucn+2 supplies an X clock-signal XCK and an inverted X clock-signal XCKB to the corresponding shift-register unit circuit Ua1 to Uan+2 in a period of time when either one of signal voltages at nodes A1, A2, . . . at the prior and subsequent stages is active.

Claims12

Dependent claims

A shift register that is used in a driving circuit to drive an electro-optical panel having a plurality of scan lines, a plurality of data lines, and pixel electrodes and switching devices which are arranged in a matrix so as to correspond to the intersections of the scan lines and the data lines, and that sequentially generates a selection signal to select the data lines or the scan lines by sequentially shifting a start pulse, the shift register comprising:

a shift device having a plurality of serially-connected shift unit circuits which sequentially shift the start pulse by synchronizing with a clock signal and an inverted clock signal, the inverted clock signal being inverted from the clock signal, and output an output signal, and which are capable of controlling a transfer direction of the start pulse in accordance with a transfer-direction signal instructing the transfer direction;
and
a clock-signal control device having a plurality of control unit circuits which are provided so as to correspond to the respective shift unit circuits and which generate a first control signal and a second control signal in accordance with the corresponding clock signal and the inverted clock signal;
the shift unit circuits each having a first logic circuit and a second logic circuit, one terminal of the first logic circuit being connected to the shift register circuit at a prior stage and another terminal of the first logic circuit being connected to an intermediate node, and one terminal of the second logic circuit being connected to the intermediate node and another terminal of the second logic circuit being connected to the shift unit circuit at a subsequent stage, and when the transfer-direction signal instructs transferring of the start pulse front a prior stage toward a subsequent stage, the first logic circuit functioning as a sampling circuit that is controlled by the first control signal and the second logic circuit functioning as a holding circuit, and when the transfer-direction signal instructs transferring of the start pulse from a subsequent stage to a prior stage, the first logic circuit functions as a holding circuit and the second logic circuit functions as a sampling circuit that is controlled by the second control signal;
and
each control unit circuit outputting the clock signal and the inverted clock signal, as the first control signal or the second control signal, to the corresponding shift unit circuit, during a selection period of time when either one of a signal voltage at the intermediate node of the shift unit circuit at the prior stage and a signal voltage at the intermediate node of the shift unit circuit at the subsequent stage becomes active.

3 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

a shift device having a plurality of serially-connected shift unit circuits which sequentially shift the start pulse by synchronizing with a clock signal and an inverted clock signal, the inverted clock signal being inverted from the clock signal, and output an output signal, and which are capable of controlling a transfer direction of the start pulse in accordance with a transfer-direction signal instructing the transfer direction;
and
a clock-signal control device having a plurality of control unit circuits which are provided so as to correspond to the respective shift unit circuits and which generate a first control signal and a second control signal in accordance with the corresponding clock signal and the inverted clock signal;
the shift unit circuits each having a first logic circuit and a second logic circuit, one terminal of the first logic circuit being connected to the shift register circuit at a prior stage and another terminal of the first logic circuit being connected to an intermediate node, and one terminal of the second logic circuit being connected to the intermediate node and another terminal of the second logic circuit being connected to the shift unit circuit at a subsequent stage, and when the transfer-direction signal instructs transferring of the start pulse front a prior stage toward a subsequent stage, the first logic circuit functioning as a sampling circuit that is controlled by the first control signal and the second logic circuit functioning as a holding circuit, and when the transfer-direction signal instructs transferring of the start pulse from a subsequent stage to a prior stage, the first logic circuit functions as a holding circuit and the second logic circuit functions as a sampling circuit that is controlled by the second control signal;
and
each control unit circuit outputting the clock signal and the inverted clock signal, as the first control signal or the second control signal, to the corresponding shift unit circuit, during a selection period of time when either one of a signal voltage at the intermediate node of the shift unit circuit at the prior stage and a signal voltage at the intermediate node of the shift unit circuit at the subsequent stage becomes active.

3 more elements