Method and apparatus for segmented, switched analog/digital converter

An analog-to-digital converter comprising:

• a comparator having a first comparator input, a second comparator input and a comparator output;
• a switched-capacitor circuit having a first and a second capacitor means arranged to be connected to the first comparator input and the second comparator input, respectively;
• a control circuit coupled between the comparator output and the switched-capacitor circuit to control an analog-to-digital conversion and deliver a digital output, wherein each of the first capacitor means and the second capacitor means in the switched-capacitor circuit further comprises;
• first and second groups of capacitor banks each having a plurality of bottom plates and a first and a second top plate, wherein the first and the second top plate is arranged to be connected to the first comparator input;
• a plurality of capacitor-switches arranged to connect the associated bottom plates of first and second groups of capacitor banks to an analog input signal, REF+, and REF−;
• a first and a second switch arranged to selectively connect the first top plate and the second top plate of each of the first and second groups of capacitor banks to the first comparator input;
• and
• a third and a fourth switch arranged to selectively connect the first top plate and the second top plate of the first and second groups of capacitor banks, respectively, to one of at least two reference voltages which the analog input signal may be sampled with respect to, wherein the third and the fourth switches arranged to turned-off and the first and the second switches arranged to connect the first top plate and the second top plate of the first and the second groups of capacitor banks, respectively, to the first comparator input substantially before start of a conversion interval, wherein the conversion interval starts substantially after completion of the sampling interval and the conversion includes one or more DAC settling intervals, and wherein the plurality of bottom plates of the first and the groups of capacitors selectively connect to one of at least two reference voltages via the plurality of capacitor-switches during each DAC interval as a function of the digital output such that each of the first and second groups of capacitor banks result in having a substantially same capacitance value.

An analog-to-digital converter comprising:

• a switched-capacitor circuit, wherein the switched-capacitor circuit comprises:
• an array of capacitors having a first and a second group of capacitors;
• a plurality of capacitor-switches coupled to the associated first and the second group of capacitors;
• third and fourth switches being operable during a sampling interval to selectively connect the first and second group of capacitors between a first input voltage and a second signal line having a second voltage and a third signal line having third voltage via the plurality of associated capacitor-switches such that the first input voltage is sampled with respect to the second voltage and the third voltage, respectively, and wherein the third and fourth switches are substantially concurrently being operable to disconnect from the second and third voltages upon completion of the sampling the first voltage by the first and second group of capacitors;
• and
• first and second switches being operable during a conversion interval to selectively connect the first and second group of capacitors to connect to a first comparator input, such that an amount of charge stored by each of said array of capacitors is equal to (Ctotal*((VDD+VSS)/2−IN)), wherein the plurality of capacitor-switches are operable during the conversion interval to select a substantially equal value of capacitance from each of the first and the second group of capacitors to provide an output signal, and wherein the Ctotal being a total capacitance value of the first and second groups of capacitor banks.

A method of sampling an analog input signal using a switched-capacitor circuit comprising:

• sampling the analog input signal onto a first group of capacitors in an array of capacitors with respect to a second voltage during a sampling interval;
• sampling the analog input signal onto a second group of capacitors in the array of capacitors with respect to a third voltage during the sampling interval;
• outputting a control signal as a function of the sampled analog input signal onto the first and the second group of capacitors;
• selectively disconnecting the second and third voltages from the first and second group of capacitors, respectively, so that the first and second group of capacitors each have a floating capacitor plate substantially before a start of a conversion interval, wherein the conversion interval starts substantially after completion of the sampling interval and includes one or more DAC settling intervals;
• and
• selectively connecting a first top plate and a second top plate of the first and second groups of capacitors, respectively, to a first comparator input during each DAC settling interval as a function of the control signal such that a plurality of bottom plates associated with the first and second groups of capacitor banks are selectively connected to one of at least two reference voltages so that each of the first and the second groups of capacitor banks result in having a substantially equal value of capacitance.