US 7,023,368 B1Granted

Digital-to-analog signal converting apparatus and method to extend usable spectrum over Nyquist frequency

AssigneeEuvis, Inc.

InventorsNeng-Haung Sheng, Cheh-Ming Jeff Liu

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Abstract

A digital-circuit return-to-zero device and method for digital-to-analog conversion is disclosed that uses an internal multiplexer alternatively selecting, or selecting in a scheduled fashion, digital input data and an expansion code. By the using the disclosed multiplexing process, where the expansion code is a null code, the usable analog spectrum of the digital-to-analog converter (DAC) extends beyond that of DACs. With the multiplexing process applied to a complementary interpolation process, the disclosed device is adapted for selective enhancement of the frequency spectrum proximate to the clock frequency. While extending the usable frequency spectrum beyond conventional DACs, the present invention, in its several embodiments, features low complexity and high portability relative to known response expansion solutions.

A direct-digital-frequency synthesizer adapted to receive a frequency code and adapted to output an analog current, the direct-digital-frequency synthesizer comprising:

a first latch adapted to receive the frequency code;
an accumulator adapted to receive the latched frequency code and a previously accumulated digital word and adapted to output a currently accumulated digital word, wherein the currently accumulated digital word upon output replaces the previously accumulated digital word for a next cycle;
a waveform determiner adapted to receive the currently accumulated digital word and output a digital data input;
a first clock signal distribution module adapted to transmit a first clock signal to the accumulator and a second clock signal to a digital-to-analog converter (DAC);
and
the digital-to-analog converter (DAC) adapted to receive the digital input data and the second clock signal and adapted to output an analog current, the DAC comprising:
an expansion code generator adapted to output a first digital expansion code;
a second latch adapted to receive the digital input data and hold the digital input data;
a multiplexer adapted to generate output by selecting the first digital expansion code from the expansion code generator during a first fraction of a clock cycle, the clock cycle comprising a plurality of cycle fractions, and by selecting the digital input data held by the second latch in a second fraction of the clock cycle, wherein the clock cycle is driven by a multiplexer clock signal;
a third latch adapted to receive the generated output of the multiplexer and adapted to hold the generated output of the multiplexer;
a current switch array adapted to receive the held multiplexer output and adapted to output analog current, and
a second clock distributor adapted to receive the second clock signal and adapted to provide a second latch module clock signal, a third latch module clock signal, and the multiplexer clock signal.

9 more elements

Abstract

Claims28