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US 7,023,281 B1Granted
Stably-biased cascode networks
AssigneeAnalog Devices, Inc.
InventorAhmed Mohamed Abdelatty Ali
Life of this patent
Estimating the term…
Abstract
Cascode bias structures are provided which enhance control of cascode biases over disturbing effects such as temperature and process variations. Because this enhanced control stabilizes the biases over these disturbing effects, the biases can be reduced to thereby expand the cascode's dynamic range and yet assure that the cascode transistors continue to operate in their proper transistor regions.
Claims32
A cascode network, comprising:
- a voltage source;
- a replica transistor;
- a compression transistor coupled between gate and drain of said replica transistor and having a gate coupled to said voltage source;
- a diode-coupled transistor coupled to the drain of said replica transistor;
- and
- a cascode arrangment of main and cascode transistors that respectively receive a bias from said replica transistor and said diode-coupled transistor.
3 more elements
A cascode network, comprising:
- a voltage source;
- a first replica transistor;
- a first compression transistor coupled between gate and drain of said first replica transistor and having a gate coupled to said voltage source;
- a second replica transistor;
- a second compression transistor coupled between gate and drain of said second replica transistor and having a gate coupled to said voltage source;
- a diode-coupled transistor coupled to the drain of said second replica transistor;
- and
- a cascode arrangment of main and cascode transistors that respectively receive a bias from said first replica transistor and said diode-coupled transistor.
5 more elements
A cascode network, comprising:
- stacked first and second voltage sources;
- stacked first and second bias circuits;
- a diode-coupled transistor coupled to said second bias circuit;
- and
- a cascode arrangment of a main transistor with first and second cascode transistors that respectively receive a bias from said first bias circuit, said second bias circuit and said diode-coupled transistor;
- wherein said bias circuits each include:
- a replica transistor;
- and
- a compression transistor coupled between gate and drain of said replica transistor and having a gate coupled to a respective one of said voltage sources.
6 more elements
A cascode network, comprising:
- stacked first and second voltage sources;
- stacked first and second bias circuits;
- stacked third and fourth bias circuits;
- a diode-coupled transistor coupled to said fourth bias circuit;
- and
- a cascode arrangement of a main transistor with first and second cascode transistors that respectively receive a bias from said first bias circuit, said second bias circuit and said diode-coupled transistor;
- wherein said bias circuits each include:
- a replica transistor;
- and
- a compression transistor coupled between gate and drain of said replica transistor and having a gate coupled to a respective one of said voltage sources.
7 more elements
Dependencies are inferred from the claim text.