US 7,023,262 B2Granted

Negative voltage generator for a semiconductor memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsJae-Yoon Sim, Jei-Hwan Yoo

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Abstract

A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Claims1

Dependent claims

A negative voltage regulator for a semiconductor device comprising:

a differential amplifier having a first input, a second input, and an output;
an output transistor coupled to the output of the differential amplifier and arranged to generate a second negative voltage from a first negative voltage;
a first voltage divider coupled to the first input of the differential amplifier;
and
a second voltage divider coupled to the second input of the differential amplifier, and adapted to drive the second input of the differential amplifier responsive to the second negative voltage;
wherein the first voltage divider comprises:
a first resistor coupled between a reference voltage and the first input of the differential amplifier, and
a second resistor coupled between the first input of the differential amplifier and a power supply terminal;
wherein the second voltage divider comprises:
a third resistor coupled between the reference voltage and the second input of the differential amplifier, and
a fourth resistor coupled between the second input of the differential amplifier and the second negative voltage;
wherein the differential amplifier comprises:
a differential pair of input transistors coupled to the first and second inputs of the differential amplifier,
a current source coupled to the differential pair of input transistors, and
a load coupled to the differential pair of input transistors;
and
wherein the output transistor has a second terminal coupled to the output of the differential amplifier.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/940,804Filed 26 Aug 2004 · division
Priority: 4 May 2001
Published: US 2005/0030086 A110 Feb 2005
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H02M 3/07
Using resistors or capacitors, e.g. potential divider: using capacitors charged and discharged alternately by semiconductor devices with control…
G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
H02M 3/071
Using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps: adapted to generate a…

Family

Application60/288,746Us provisional application · filed 4 May 2001
Application09/901,930Parent of this division · filed 9 Jul 2001
Application10/422,534Parent of this division · filed 23 Apr 2003
US 2005/0030086 A1Pre-grant publication · published 10 Feb 2005
US 2002/0171470 A1Published application
US 2003/0197546 A1Published application
US 7,336,121 B2Related patent
US 7,023,262 B2This patent

From the US filing history. Foreign family members aren’t listed.