Differential coder for electrical signals

A differential coder (10) for electrical signals, comprising:

• control means (21, 22) adapted:
• to receive a clock signal (CK) defining a bit time and an input binary data signal (DATA) substantially synchronized with the clock signal and defining a sequence of first and second values (N1, N2) in accordance with a non return to zero format, and
• to supply a master control signal (A) defined by a stable level (ST) and by a change of level (P1 to P11) that is triggered when the input binary data signal corresponds to the second value, and
• a bistable T controlled by the control means and adapted to supply an output binary data signal (S, S*) having a low level (Na) and a high level (Nb) and which is defined by:
• the same binary state (‘0’, ‘1’) over two successive bit times when the master control signal is maintained at the stable level, and
• a change of state associated with a change (C1 to C10) from either the low level or the high level to the high level or the low level triggered by said change of level, respectively
• which coder is characterized in that the bistable T comprises a master bistable (11) followed by a slave bistable (12) each having a main control input (E1, E2),
• and in that the differential coder is integrated and said control means comprise:
• a first circuit (21) dedicated to the master bistable and adapted to supply said master control signal (A) which is injected into the main control input of the master bistable, and
• a second circuit (22) dedicated to the slave bistable, controlled by said clock signal (CK) and adapted to supply a slave control signal (CK2) that is representative of a signal complementary to the clock signal and injected into the main control input of the slave bistable.