Latch with data jitter free clock load

A digital latch with a data jitter free clock load, comprising:

• a latch circuit having first and second latch data inputs, first and second latch data outputs, and a clock signal input, said latch circuit having a load value relative to a clock driver, said load value changing in response to a change in a state of the data received at said first and second data inputs;
• a first sense amplifier having first and second data inputs, first and second outputs, and a clock signal input;
• and
• a second sense amplifier having first and second data inputs, first and second outputs, and a clock signal input;
• said first output of said first sense amplifier being connected to said first latch data input;
• said second output of said first sense amplifier being connected to said second latch data input;
• said first output of said second sense amplifier being connected to said first latch data output;
• said second output of said second sense amplifier being connected to said second latch data output;
• said first input of said first sense amplifier being connected to said first input of said second sense amplifier;
• said second input of said first sense amplifier being connected to said second input of said second sense amplifier.

A digital latch with a data jitter free clock load, comprising:

• a first inverter stage connected to a first input, said first inverter stage including a first inverter stage first floating node and a first inverter stage first pre-charging device, said first inverter stage including a first inverter stage second floating node and a first inverter stage second pre-charging device;
• a second inverter stage connected to a second input, said second inverter stage including a second inverter stage first floating node and a second inverter stage first pre-charging device, said second inverter stage including a second inverter stage second floating node and a second inverter stage second pre-charging device;
• and
• a latch circuit having first and second latch data inputs;
• said first latch data input being operatively connected to said first inverter stage;
• said second latch data input being operatively connected to said second inverter stage;
• said latch circuit having first and second latch data outputs;
• said first inverter stage first pre-charging device pre-charging said first inverter stage first floating node to a first pre-determined value each clock cycle;
• said second inverter stage first pre-charging device pre-charging said second inverter stage first floating node to said first pre-determined value each clock cycle.

A digital latch with a data jitter free clock load, comprising:

• a first inverter stage connected to a first input, said first inverter stage including a first inverter stage first floating node and a first inverter stage first pre-charging device, said first inverter stage including a first inverter stage second floating node and a first inverter stage second pre-charging device;
• a second inverter stage connected to a second input, said second inverter stage including a second inverter stage first floating node and a second inverter stage first pre-charging device, said second inverter stage including a second inverter stage second floating node and a second inverter stage second pre-charging device;
• and
• a latch circuit having first and second latch data inputs;
• said latch circuit having first and second latch data outputs;
• said first inverter stage first floating node being formed at a common connection between a first inverter stage first inverting device, a first inverter stage first clock transistor, and said first inverter stage first pre-charging device;
• said second inverter stage first floating node being formed at a common connection between a second inverter stage first inverting device, a second inverter stage first clock transistor, and said second inverter stage first pre-charging device;
• said first inverter stage including a first inverter stage second floating node formed at a common connection between a first inverter stage second inverting device, a first inverter stage second clock transistor, and said first inverter stage second pre-charging device;
• said second inverter stage including a second inverter stage second floating node formed at a common connection between a second inverter stage second inverting device, a second inverter stage second clock transistor, and said second inverter stage second pre-charging device;
• said output of first inverter stage first clock transistor being connected to said first latch data input;
• said output of second inverter stage first clock transistor being connected to said second latch data input;
• said first inverter stage first pre-charging device pre-charging said first inverter stage first floating node to a first pre-determined value when said first inverter stage first clock transistor is OFF;
• said second inverter stage first pre-charging device pre-charging said second inverter stage first floating node to said first pre-determined value when said second inverter stage first clock transistor is OFF.