Programmable bandwidth during start-up for phase-lock loop
AssigneeIntersil Americas Inc.
InventorShyng Duan Chen
Life of this patent
Estimating the term…
Abstract
A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.
Claims21
A phase-lock loop comprising:
- an oscillator having an output oscillator signal whose frequency is related to a received error-correction signal:
- a phase-frequency circuit receiving the oscillator signal and a reference signal and generating at a controllable rate error-correction pulses based on a phase difference between the oscillator signal and the reference signal;
- a filter generating the error-correction signal from the error-correction pulses, the filter including a capacitor;
- and
- a rate selector coupled to the capacitor and to the phase-frequency circuit, monitoring a charge on the capacitor, and controlling the rate at which the phase-frequency circuit generates the error-correction pulses to equal any one of more than two rates as a function of the charge on the capacitor.
A phase-lock loop comprising:
- an oscillator having an output oscillator signal whose frequency is related to a received error-correction signal:
- a phase-frequency circuit receiving the oscillator signal and a reference signal and generating at a controllable rate the error-correction pulses based on the a phase difference between the oscillator signal and the reference signal;
- a filter generating the error-correction signal from the error-correction pulses, the filter including a capacitor;
- a rate selector coupled to the capacitor and to the phase-frequency circuit, monitoring a charge on the capacitor, and controlling the rate at which the phase-frequency circuit generates of the error-correction pulses as a function of the charge on the capacitor;
- wherein the phase-detector circuit determines the phase difference between the oscillator and reference signals during phase-comparison cycles;
- wherein the rate selector sets the rate of the error-connection pulses to once per each of the comparison cycles until the charge equals a first threshold value, and decreases the rate to less than once per each of the comparison cycles after the charge equals the first threshold value;
- wherein the rate selector includes a cycle counter to count the comparison cycles;
- and
- wherein the rate selector uses the counter to set the decreasing rates of the error-correction pulses.
A phase-lock loop comprising:
- an oscillator having an output oscillator signal whose frequency is related to a received error-correction signal:
- a phase-frequency circuit receiving the oscillator signal and a reference signal and generating at a controllable rate error-correction pulses based on a phase difference between the oscillator signal and the reference signal;
- a filter generating the error-correction signal from the error-correction pulses, the filter including a capacitor;
- a rate selector coupled to the capacitor and to the phase-frequency circuit, monitoring a charge on the capacitor, and controlling the rate at which the phase-frequency circuit generates the error-correction pulses as a function of the charge on the capacitor;
- wherein the phase-detector circuit determines the phase difference between the oscillator and reference signals during comparison cycles;
- wherein the rate selector includes a counter to count the comparison cycles;
- and
- wherein the rate selector causes the phase-frequency circuit to generate the error-correction pulses at a rate that is related to the count of the counter and to the capacitor voltage.
Dependencies are inferred from the claim text.