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US 7,023,240 B2Granted
Data-driven clock gating for a sequential data-capture device
AssigneeTexas Instruments Incorporated
InventorTony T Elappuparackal
Life of this patent
Estimating the term…
Abstract
A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.
Claims12
A processor, comprising:
- a core;
- a memory coupled to said core via a multi-bit bus;
- and
- a register circuit which captures data from said bus including:
- a plurality of flip-flops, each flip-flop associated with a bit on said bus and receiving said bit as an input data bit and producing an output data bit upon assertion of a gated clock signal;
- comparison logic coupled to each of said flip-flops that receives the input and output data bits from each of said flip-flops and compares the logic states of respective input and output data bits and, if the logic states of any of said bits do not match, asserts an enable signal to indicate that one of said input data bits has changed state;
- and
- clock logic that receives said enable signal and an external clock signal and generates the gated clock signal based on the logic state of the enable signal and external clock signal.
5 more elements
A processor, comprising:
- a core;
- a memory coupled to said core via a multi-bit bus;
- and
- a register circuit which captures data from said bus including:
- a flip-flop associated with a bit on said bus and receiving said bit as an input data bit and producing an output data bit upon assertion of a gated clock signal;
- comparison logic coupled to said flip-flop that receives the input and output data bits from said flip-flop and compares the logic states of said input and output data bits and, if the logic states of said bits do not match, asserts an enable signal to indicate that said input data bit has changed state;
- and
- clock logic that receives said enable signal and an external clock signal and generates the gated clock signal based on the logic state of the enable signal and external clock signal, wherein the clock logic comprises a clock latch that receives the enable signal as input signal and latches the state of the enable signal upon assertion of the external clock signal.
5 more elements
A processor, comprising:
- a core;
- a memory coupled to said core via a multi-bit bus;
- and
- a register circuit which captures data from said bus including:
- a flip-flop associated with a bit on said bus and receiving said bit as an input data bit and producing an output data bit upon assertion of a gated clock signal;
- comparison logic coupled to said flip-flop that receives the input and output data bits from said flip-flop and compares the logic states of said input and output data bits and, if the logic states of said bits do not match, asserts an enable signal to indicate that said input data bit has changed state;
- and
- clock logic that receives said enable signal and an external clock signal and generates the gated clock signal based on the logic state of the enable signal and external clock signal, wherein said clock logic receives an external data valid signal and asserts the gated clock signal only when both the data valid signal and the enable signals are asserted.
5 more elements
Dependencies are inferred from the claim text.